A method for automatic design error location and correction in combinational logic circuits Ayman M. WahbaDominique Borrione OriginalPaper Pages: 113 - 127
Fault simulation for mixed-signal systems Pascal CaunegreClaude Abraham OriginalPaper Pages: 143 - 152
A new reconfigurable Test Vector Generator for built-in self-test applications Samir BoubezariBozena Kaminska OriginalPaper Pages: 153 - 164
A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST Michael GoesselEgor S. Sogomonyan OriginalPaper Pages: 165 - 177
Monitoring machine based synthesis technique for concurrent error detection in finite state machines R. A. ParekhjiG. VenkateshS. D. Sherlekar OriginalPaper Pages: 179 - 201
SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis Manoj Sachdev OriginalPaper Pages: 203 - 214
An efficient built-in self test method for robust path delay fault testing Ioannis VoyiatzisAntonis PaschalisConstantin Halatsis OriginalPaper Pages: 219 - 222