1. Editorial

   EditorialNotes Pages: 5 - 5

2. New editorial board members

   Legacy Pages: 7 - 7

3. Reviewers

   Legacy Pages: 8 - 8

4. Sequential circuit test generation using dynamic justification equivalence

   • Xinghao Chen
   • Michael L. Bushnell

   OriginalPaper Pages: 9 - 33

5. Bridging defects resistance in the metal layer of a CMOS process

   • R. Rodríguez-Montañés
   • E. M. J. G. Bruls
   • J. Figueras

   OriginalPaper Pages: 35 - 46

6. Statistical estimation of delay fault detectabilities and fault grading

   • Zaifu Zhang
   • Robert D. Mcleod
   • Gregory E. Bridges

   OriginalPaper Pages: 47 - 60

7. The dangers of simplistic delay models

   • David M. Wessels
   • Jon C. Muzio

   OriginalPaper Pages: 61 - 69

8. Balance testing and balance-testable design of logic circuits

   • Krishnendu Chakrabarty
   • John P. Hayes

   OriginalPaper Pages: 71 - 86

9. Diagnostic simulation of stuck-at faults in combinational circuits

   • Sreejit Chakravarty
   • Yiming Gong
   • Srikanth Venkataraman

   OriginalPaper Pages: 87 - 97

10. Third International Test Synthesis Workshop

    Report Pages: 99 - 99

11. 5th IEEE North Atlantic Test Workshop

    Report Pages: 100 - 100

12. MCM III Test Advanced Technology Workshop

    Report Pages: 101 - 101

13. ETW'96 IEEE European Test Workshop

    Report Pages: 102 - 102

14. 2nd IEEE International On-Line Testing Workshop

    Report Pages: 103 - 103

15. 14th IEEE VLSI Test Symposium

    Report Pages: 104 - 104