1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 147 - 147

2. New editorial board members

   EditorialNotes Pages: 149 - 150

3. Journal of electronic testing: Theory and applications

   Legacy Pages: 151 - 152

4. Testing VLSI regular arrays

   • W. P. Marnane
   • W. R. Moore

   Testing of Array Architecture Pages: 153 - 177

5. Testability of artificial neural networks: A behavioral approach

   • Vincenzo Piuri
   • Mariagiovanna Sami
   • Donatella Sciuto

   Testing of Neural Networks Pages: 179 - 190

6. Reducing the CMOS RAM test complexity withI _DDQ and voltage testing

   • Manoj Sachdev

   Memory Test Pages: 191 - 202

7. TIES: A testability increase expert system for VLSI design

   • G. Buonanno
   • F. Fummi
   • D. Sciuto

   Design for Testability Pages: 203 - 217

8. Self-timed is self-checking

   • Ilana David
   • Ran Ginosar
   • Michael Yoeli

   Self-test and Self-checking Circuits Pages: 219 - 228

9. Avoiding linear dependencies in LFSR test pattern generators

   • Dimitrios Kagaris
   • Spyros Tragoudas

   Self-test and Self-checking Circuits Pages: 229 - 241

10. Evaluating the safety of self-checking circuits

    • Shujian Zhang
    • Jon C. Muzio

    Self-test and Self-checking Circuits Pages: 243 - 253

11. Minimal cost one-dimensional linear hybrid cellular automata of degree through 500

    • Kevin Cattell
    • Shujian Zhang

    Jetta Letter Pages: 255 - 258

12. Special issue on test synthesis

    Call for Papers Pages: 259 - 259