Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults C. MetraM. FavalliB. Riccò Self-checking Circuits Pages: 7 - 22
Transient power supply current monitoring—A new test method for CMOS VLSI circuits Shyang-Tai SuRafic Z. MakkiTroy Nagle New Test Methodology Pages: 23 - 43
Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits Konstantin KeutnerErwin Trischler Test Generation Pages: 45 - 58
A switch-level test generation system for synchronous and asynchronous circuits Kent L. EinspahrSharad C. Seth Test Generation Pages: 59 - 73
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes D. LambidonisV. K. AgarwalD. Xavier Self-test Systems Pages: 75 - 84
HIST: A hierarchical self test methodology for chips, boards, and systems Oliver F. HaberlThomas Kropf Self-test Systems Pages: 85 - 106
A structure and technique for pseudorandom-based testing of sequential circuits Fidel MuradaliTakao NishidaTsuguo Shimizu Self-test Systems Pages: 107 - 115
Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes Soon Fatt Yoon Reliability Test Pages: 117 - 125
Constrained state assignment of easily testable FSMs María J. AvedilloJosé M. QuintanaJosé L. Huertas JETTA Letters Pages: 133 - 138
Authors' reply to comments on “Aliasing Properties of Circular MISRs” G. EdirisooriyaJ. P. Robinson JETTA Letters Pages: 141 - 142