1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 5 - 6

2. Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

   • C. Metra
   • M. Favalli
   • B. Riccò

   Self-checking Circuits Pages: 7 - 22

3. Transient power supply current monitoring—A new test method for CMOS VLSI circuits

   • Shyang-Tai Su
   • Rafic Z. Makki
   • Troy Nagle

   New Test Methodology Pages: 23 - 43

4. Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits

   • Konstantin Keutner
   • Erwin Trischler

   Test Generation Pages: 45 - 58

5. A switch-level test generation system for synchronous and asynchronous circuits

   • Kent L. Einspahr
   • Sharad C. Seth

   Test Generation Pages: 59 - 73

6. A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes

   • D. Lambidonis
   • V. K. Agarwal
   • D. Xavier

   Self-test Systems Pages: 75 - 84

7. HIST: A hierarchical self test methodology for chips, boards, and systems

   • Oliver F. Haberl
   • Thomas Kropf

   Self-test Systems Pages: 85 - 106

8. A structure and technique for pseudorandom-based testing of sequential circuits

   • Fidel Muradali
   • Takao Nishida
   • Tsuguo Shimizu

   Self-test Systems Pages: 107 - 115

9. Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes

   • Soon Fatt Yoon

   Reliability Test Pages: 117 - 125

10. Current testing in dynamic CMOS circuits

    • J. Figueras
    • M. Renovell

    JETTA Letters Pages: 127 - 131

11. Constrained state assignment of easily testable FSMs

    • María J. Avedillo
    • José M. Quintana
    • José L. Huertas

    JETTA Letters Pages: 133 - 138

12. Comments on “Aliasing Properties of Circular MISRs”

    • Slawomir Pilarski

    JETTA Letters Pages: 139 - 140

13. Authors' reply to comments on “Aliasing Properties of Circular MISRs”

    • G. Edirisooriya
    • J. P. Robinson

    JETTA Letters Pages: 141 - 142