1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 07 February 2018 Pages: 1 - 1

2. New Editor – 2018

   Announcement 08 February 2018 Pages: 3 - 3

   

3. Test Technology Newsletter

   News 15 January 2018 Pages: 5 - 6

4. Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints

   • Mostafa Salehi
   • Ali Azarpeyvand
   • Armin Hajaboutalebi Aboutalebi

   OriginalPaper 01 March 2018 Pages: 7 - 14

   

5. FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC

   • Xiaozhi Du
   • Dongyang Luo
   • Shuhuan Liu

   OriginalPaper 03 January 2018 Pages: 15 - 25

   

6. NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

   • Yang Yu
   • Jie Liang
   • Xiyuan Peng

   OriginalPaper 01 February 2018 Pages: 27 - 41

   

7. Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC

   • Davide Appello
   • Paolo Bernardi
   • Federico Venini

   OriginalPaper 03 February 2018 Pages: 43 - 52

   

8. Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

   • Toral Shah
   • Anzhela Matrosova
   • Virendra Singh

   OriginalPaper 01 February 2018 Pages: 53 - 65

   

9. Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

   • Michael A. Skitsas
   • Chrysostomos A. Nicopoulos
   • Maria K. Michael

   OriginalPaper 27 January 2018 Pages: 67 - 81

   

10. Automation of Test Program Synthesis for Processor Post-silicon Validation

    • Vasudevan Madampu Suryasarman
    • Santosh Biswas
    • Aryabartta Sahu

    OriginalPaper 07 February 2018 Pages: 83 - 103