Guest Editorial Salvador MirTim ChengAndrew Richardson EditorialNotes 19 January 2007 Pages: 311 - 311
Test Development Through Defect and Test Escape Level Estimation for Data Converters Carsten WegenerMichael Peter Kennedy OriginalPaper 23 November 2006 Pages: 313 - 324
A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting Luis RolíndezSalvador MirJean-Louis Carbonéro OriginalPaper 18 January 2007 Pages: 325 - 335
Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation Heinz MattesStéphane KirmserSebastian Sattler OriginalPaper 30 November 2006 Pages: 337 - 350
A First Step for an INL Spectral-Based BIST: The Memory Optimization V. KerzérhoS. BernardJ. M. Janik OriginalPaper 08 December 2006 Pages: 351 - 357
Investigation into the Use of Hybrid Solutions for ΣΔ A/D Converter Testing K. GeorgopoulosA. LechnerA. Richardson OriginalPaper 18 January 2007 Pages: 359 - 370
Towards Fault-Tolerant RF Front Ends Tejasvi DasAnand GopalanP. R. Mukund OriginalPaper 18 January 2007 Pages: 371 - 386
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines Jiun-Lang Huang OriginalPaper 22 November 2006 Pages: 387 - 398
Structural Fault Modeling and Fault Detection Through Neyman–Pearson Decision Criteria for Analog Integrated Circuits Amir ZjajoJose Pineda de GyvezGuido Gronthoud OriginalPaper 22 November 2006 Pages: 399 - 409
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X–Y Zoning Method: Case Study Yukiya Miura OriginalPaper 07 December 2006 Pages: 411 - 423
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation Michel MorneauAbdelhakim Khouas OriginalPaper 22 November 2006 Pages: 425 - 436
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing M. A. DomínguezJ. L. AusínG. Torelli OriginalPaper 30 November 2006 Pages: 437 - 448
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays Amit LaknaurSai Raghuram DurbhaHaibo Wang OriginalPaper 23 November 2006 Pages: 449 - 462
Embedded System Level Self-Test for Mixed-Signal IO Verification V. Loukusa OriginalPaper 01 December 2006 Pages: 463 - 470
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects Xiangdong XuanAdit D. SinghAbhijit Chatterjee OriginalPaper 22 November 2006 Pages: 471 - 482