Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits Bipul C. PaulKaushik Roy OriginalPaper Pages: 115 - 124
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability Hafizur RahamanDebesh K. DasBhargab B. Bhattacharya OriginalPaper Pages: 125 - 142
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2 m ) Chiou-Yng LeeChe Wun ChiouJim-Min Lin OriginalPaper Pages: 143 - 150
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults Yu-Chiun LinShi-Yu Huang OriginalPaper Pages: 151 - 159
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs Patrick GirardOlivier HéronMichel Renovell OriginalPaper Pages: 161 - 172
Crosstalk Induced Fault Analysis and Test in DRAMs Zemo YangSamiha Mourad OriginalPaper Pages: 173 - 187
Electro-thermal Stimuli for MEMS Testing in FSBM Technology N. DumasF. AzaïsP. Nouet OriginalPaper Pages: 189 - 198
Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems Fei SuSule OzevKrishnendu Chakrabarty OriginalPaper Pages: 199 - 210