1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 5 - 5

2. Test Technology Newsletter

   OriginalPaper Pages: 7 - 8

3. New JETTA Editors, 2006

   • Bashir M. Al-Hashimi
   • Dimitris Gizopoulos
   • Adit D. Singh

   OriginalPaper Pages: 9 - 10

4. Scaling of i _DDT Test Methods for Random Logic Circuits

   • Ali Chehab
   • Saurabh Patel
   • Rafic Makki

   OriginalPaper Pages: 11 - 22

5. Theorems for Fault Collapsing in Combinational Circuits

   • Audhild Vaaje

   OriginalPaper Pages: 23 - 36

6. An Efficient Dictionary Organization for Maximum Diagnosis

   • Sunghoon Chun
   • Sangwook Kim
   • Sungho Kang

   OriginalPaper Pages: 37 - 48

7. Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly

   • Zhen Shi
   • Peter Sandborn

   OriginalPaper Pages: 49 - 60

8. Automatic Test Pattern Generation for Resistive Bridging Faults

   • Piet Engelke
   • Ilia Polian
   • Bernd Becker

   OriginalPaper Pages: 61 - 69

9. A Self Test Program Design Technique for Embedded DSP Cores

   • Hani Rizk
   • Chris Papachristou
   • Francis Wolff

   OriginalPaper Pages: 71 - 87

10. A Gated Clock Scheme for Low Power Testing of Logic Cores

    • Yannick Bonhomme
    • Patrick Girard
    • Arnaud Virazel

    OriginalPaper Pages: 89 - 99

11. Modulo p = 3 Checking for a Carry Select Adder

    • V. Ocheretnij
    • M. Gössel
    • D. Marienfeld

    OriginalPaper Pages: 101 - 107