1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 459 - 459

2. The Newsletter of Test Technology Council of the IEEE Computer Society

   • Bruce Kim

   Letter Pages: 461 - 462

3. Defect Detection Using Quiescent Signal Analysis

   • Chintan Patel
   • Abhishek Singh
   • Jim Plusquellic

   OriginalPaper Pages: 463 - 483

4. Incremental Design Debugging in a Logic Synthesis Environment

   • Andreas Veneris
   • Jiang Brandon Liu

   OriginalPaper Pages: 485 - 494

5. Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

   • Andreas Veneris
   • Robert Chang
   • Sep Seyedi

   OriginalPaper Pages: 495 - 502

6. A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

   • Santosh Biswas
   • Siddhartha Mukhopadhyay
   • Amit Patra

   OriginalPaper Pages: 503 - 537

7. Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 ^m )

   • Chiou-Yng Lee
   • Che Wun Chiou
   • Jim-Min Lin

   OriginalPaper Pages: 539 - 549

8. Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

   • Luigi Dilillo
   • Patrick Girard
   • Magali Hage-Hassan

   OriginalPaper Pages: 551 - 561