Volume 21, Issue 4

August 2005

Special Issue on On-Line-Testing and Fault Tolerance

Issue Editors:

11 articles in this issue

Editorial
Vishwani D. Agrawal, Editor-in-Chief
EditorialNotes Pages: 343 - 343
Test Technology Newsletter
Bruce Kim, Editor
Announcement Pages: 345 - 345
Guest Editorial
Cecilia Metra, Régis Leveugle
EditorialNotes Pages: 347 - 347
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
D. Barros Júnior
M. Rodriguez-Irago
J. P. Teixeira
OriginalPaper Pages: 349 - 363
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation
A. Ammari
K. Hadjiat
R. Leveugle
OriginalPaper Pages: 365 - 376
Self-Checking Voter for High Speed TMR Systems
José Manuel Cazeaux
Daniele Rossi
Cecilia Metra
OriginalPaper Pages: 377 - 389
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes^∗
Steffen Tarnick
OriginalPaper Pages: 391 - 404
The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit
C. Jeffrey
R. Cutajar
S. Riches
OriginalPaper Pages: 405 - 416
Low Cost On-Line Testing Strategy for RF Circuits
Marcelo Negreiros
Luigi Carro
Altamiro A. Susin
OriginalPaper Pages: 417 - 427
A Comparative Evaluation of Designs for Reliable Memory Systems
G. C. Cardarilli
F. Lombardi
A. Salsano
OriginalPaper Pages: 429 - 444
Memory Defect Tolerance Architectures for Nanotechnologies
Michael Nicolaidis
Lorena Anghel
Nadir Achouri
OriginalPaper Pages: 445 - 455

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