Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation Zainalabedin NavabiShahrzad MirkhaniFabrizio Lombardi OriginalPaper Pages: 575 - 589
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST* Michael GoesselKrishnendu ChakrabartyAndreas Leininger OriginalPaper Pages: 611 - 622
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs Sunil Rafeeque K.P.Vinita Vasudevan OriginalPaper Pages: 623 - 638
Scan Test Strategy for Asynchronous-Synchronous Interfaces Octavian PetreHans G. Kerkhoff OriginalPaper Pages: 639 - 645
Power-Driven Routing-Constrained Scan Chain Design Y. BonhommeP. GirardS. Pravossoudovitch OriginalPaper Pages: 647 - 660
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs Seok-Bum Ko OriginalPaper Pages: 661 - 665
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression Lei LiKrishnendu Chakrabarty OriginalPaper Pages: 667 - 670