Volume 20, Issue 5

October 2004

On-line Testing

Issue Editors:

12 articles in this issue

Editorial
Vishwani D. Agrawal
Editorial Introduction Pages: 459 - 459
Test Technology Technical Council Newsletter
P. Prinetto
News Pages: 461 - 462
Guest Editorial
Cecilia Metra
Matteo Sonza Reorda
Editorial Introduction Pages: 463 - 463
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes
Steffen Tarnick
OriginalPaper Pages: 465 - 477
An Analog Checker with Input-Relative Tolerance for Duplicate Signals
Haralampos-G. D. Stratigopoulos
Yiorgos Makris
OriginalPaper Pages: 479 - 488
Efficient Realization of Parity Prediction Functions in FPGAs
Seok-Bum Ko
Jien-Chung Lo
OriginalPaper Pages: 489 - 499
Model for Transient Fault Susceptibility of Combinational Circuits
Martin Omaña
Daniele Rossi
Cecilia Metra
OriginalPaper Pages: 501 - 509
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
M. Sonza Reorda
M. Violante
OriginalPaper Pages: 511 - 521
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
S. Matakias
Y. Tsiatouhas
Th. Haniotakis
OriginalPaper Pages: 523 - 531
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors
André K. Nieuwland
Richard P. Kleihorst
OriginalPaper Pages: 533 - 542
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
B. Alorda
V. Canals
J. Segura
OriginalPaper Pages: 543 - 552
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Amir Rajabzadeh
Seyed Ghassem Miremadi
Mirzad Mohandespour
OriginalPaper Pages: 553 - 567

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