1. Editorial

   • Vishwani D. Agrawal

   Editorial Introduction Pages: 127 - 127

2. New Editorial Board Members

   Editorial Board Pages: 129 - 130

3. Test Technology Technical Council Newsletter

   • P. Prinetto

   News Pages: 131 - 132

4. A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

   • L. Dermentzoglou
   • Y. Tsiatouhas
   • A. Arapoyanni

   OriginalPaper Pages: 133 - 142

5. Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours

   • R. Rodríguez-Montañés
   • D. Muñoz
   • J. Figueras

   OriginalPaper Pages: 143 - 153

6. A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

   • M.H. Tehranipour
   • S.M. Fakhraie
   • M.R. Movahedin

   OriginalPaper Pages: 155 - 168

7. Testability Trade-Offs for BIST Data Paths

   • Nicola Nicolici
   • Bashir M. Al-Hashimi

   OriginalPaper Pages: 169 - 179

8. Scalable Delay Fault BIST for Use with Low-Cost ATE

   • Ilia Polian
   • Bernd Becker

   OriginalPaper Pages: 181 - 197

9. Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

   • Anshuman Chandra
   • Krishnendu Chakrabarty

   OriginalPaper Pages: 199 - 212

10. Scan Latch Design for Test Applications

    • Amit M. Sheth
    • Jacob Savir

    OriginalPaper Pages: 213 - 216