1. Editorial

   EditorialNotes Pages: 313 - 313

2. Bounding fault detection probabilities in combinational circuits

   • George Markowsky

   OriginalPaper Pages: 315 - 323

3. Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

   • Warren H. Debany Jr.
   • Carlos R. P. Hartmann

   OriginalPaper Pages: 325 - 338

4. The minimum test set problem for circuits with nonreconvergent fanout

   • Irith Pomeranz
   • Zvi Kohavi

   OriginalPaper Pages: 339 - 349

5. Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

   • Abhijit Chatterjee
   • Jacob A. Abraham

   OriginalPaper Pages: 351 - 372

6. Analysis of Hamming count compaction scheme

   • Wen-Ben Jone
   • Anita Gleason

   OriginalPaper Pages: 373 - 384

7. Model-based reasoning for electron-beam debugging of VLSI circuits

   • Meryem Marzouki

   OriginalPaper Pages: 385 - 394

8. Checkpoints in irredundant two-level combinational circuits

   • Jwu E. Chen
   • Chung Len Lee
   • Wen Zen Shen

   Letter Pages: 395 - 397

9. Call for papers

   Announcement Pages: 399 - 399