Combined probabilistic testability calculation and compact test generation for PLAs Bjørg ReppenEinar J. Aas OriginalPaper Pages: 215 - 227
Fault modeling and fault equivalence in CMOS technology Marie -Lise FlottesChristian LandraultSerge Pravossoudovitch OriginalPaper Pages: 229 - 241
Exact ordered binary decision diagram size when representing classes of symmetric functions Don E. RossKenneth M. ButlerM. Ray Mercer OriginalPaper Pages: 243 - 259
A methodology for the design of SFS/SCD circuits for a class of unordered codes Sandeep PageyS. D. SherlekarG. Venkatesh OriginalPaper Pages: 261 - 277
Comments on “optimizing error masking in BIST by output data modification” R. Kh. Latypov JETTA Letter Pages: 307 - 308