1. Editorial

   EditorialNotes Pages: 213 - 213

2. Combined probabilistic testability calculation and compact test generation for PLAs

   • Bjørg Reppen
   • Einar J. Aas

   OriginalPaper Pages: 215 - 227

3. Fault modeling and fault equivalence in CMOS technology

   • Marie -Lise Flottes
   • Christian Landrault
   • Serge Pravossoudovitch

   OriginalPaper Pages: 229 - 241

4. Exact ordered binary decision diagram size when representing classes of symmetric functions

   • Don E. Ross
   • Kenneth M. Butler
   • M. Ray Mercer

   OriginalPaper Pages: 243 - 259

5. A methodology for the design of SFS/SCD circuits for a class of unordered codes

   • Sandeep Pagey
   • S. D. Sherlekar
   • G. Venkatesh

   OriginalPaper Pages: 261 - 277

6. Constrained parity testing

   • P. K. Lui
   • J. C. Muzio

   OriginalPaper Pages: 279 - 291

7. Redundancy effect on yield of binary tree RAMs

   • B. Ciciani

   OriginalPaper Pages: 293 - 306

8. Comments on “optimizing error masking in BIST by output data modification”

   • R. Kh. Latypov

   JETTA Letter Pages: 307 - 308

9. Erratum

   Erratum Pages: 309 - 309