1. Editorial

   • Vishwani D. Agrawal

   Editorial Board Pages: 363 - 363

2. Test Technology Technical Council Newsletter

   • A. Ivanov

   Legacy Pages: 365 - 366

3. Guest Editorial

   • Christian Landrault

   Editorial Board Pages: 367 - 367

4. On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up

   • Camelia Hora
   • Rene Segers
   • Maurice Lousberg

   OriginalPaper Pages: 369 - 376

5. Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

   • M. Renovell
   • J.M. Gallière
   • Y. Bertrand

   OriginalPaper Pages: 377 - 386

6. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting

   • Jonathan Bradford
   • Hartmut Delong
   • Bernd Becker

   OriginalPaper Pages: 387 - 395

7. Synchronous Full-Scan for Asynchronous Handshake Circuits

   • Frank te Beest
   • Ad Peeters
   • Hans Kerkhoff

   OriginalPaper Pages: 397 - 406

8. Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips

   • Sandeep Kumar Goel
   • Bart Vermeulen

   OriginalPaper Pages: 407 - 416

9. Multi-TAP Controller Architecture for Digital System Chips

   • Bart Vermeulen
   • Tom Waayers
   • Sjaak Bakker

   OriginalPaper Pages: 417 - 424

10. A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

    • Sandeep Kumar Goel
    • Erik Jan Marinissen

    OriginalPaper Pages: 425 - 435

11. Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

    • Xiao Liu
    • Michael S. Hsiao
    • Paul J. Thadikaran

    OriginalPaper Pages: 437 - 445

12. On Selecting Testable Paths in Scan Designs

    • Yun Shao
    • Sudhakar M. Reddy
    • Seiji Kajihara

    OriginalPaper Pages: 447 - 456

13. Reducing Average and Peak Test Power Through Scan Chain Modification

    • Ozgur Sinanoglu
    • Ismet Bayraktaroglu
    • Alex Orailoglu

    OriginalPaper Pages: 457 - 467

14. On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

    • S. Bernard
    • F. Azaïs
    • M. Renovell

    OriginalPaper Pages: 469 - 479

15. Investigations for Minimum Invasion Digital Only Built-In “Ramp” Based Test Techniques for Charge Pump PLL's

    • Martin John Burbidge
    • Frederic Poullet
    • Andrew Richardson

    OriginalPaper Pages: 481 - 490