1. Editorial

   • Vishwani D. Agrawal

   Editorial Board Pages: 219 - 219

2. Test Technology Technical Council Newsletter

   • A. Ivanov

   Legacy Pages: 221 - 222

3. A Ring Architecture Strategy for BIST Test Pattern Generation

   • C. Fagot
   • O. Gascuel
   • C. Landrault

   OriginalPaper Pages: 223 - 231

4. LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds

   • Dimitri Kagaris
   • Spyros Tragoudas

   OriginalPaper Pages: 233 - 244

5. Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

   • Hao-Yung Lo
   • Hsiu-Feng Lin
   • Chia-Cheng Liu

   OriginalPaper Pages: 245 - 269

6. Modeling Fault Coverage of Random Test Patterns

   • Hailong Cui
   • Sharad C. Seth
   • Shashank K. Mehta

   OriginalPaper Pages: 271 - 284

7. Easily Testable Cellular Carry Lookahead Adders

   • Dimitris Gizopoulos
   • Mihalis Psarakis
   • Yervant Zorian

   OriginalPaper Pages: 285 - 298

8. A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

   • Muhammad Nummer
   • Manoj Sachdev

   OriginalPaper Pages: 299 - 314

9. A Novel Built-In Self-Repair Approach for Embedded RAMs

   • Shyue-Kung Lu

   OriginalPaper Pages: 315 - 324

10. Replacing I _DDQ Testing: With Variance Reduction

    • C. Thibeault

    OriginalPaper Pages: 325 - 340

11. Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I _DDQ Testing

    • Oleg Semenov
    • Arman Vassighi
    • Manoj Sachdev

    OriginalPaper Pages: 341 - 352

12. Thermal Testing of Analogue Integrated Circuits: A Case Study

    • J. Altet
    • A. Ivanov
    • A. Wong

    OriginalPaper Pages: 353 - 357