1. Editorial

   • Vishwani D. Agrawal

   Editorial Introduction Pages: 95 - 95

2. New Editorial Board Members

   Editorial Board Pages: 97 - 98

3. Test Technology Technical Council Newsletter

   • André Ivanov

   News Pages: 99 - 100

4. Guest Editorial

   • André Ivanov

   Editorial Board Pages: 101 - 102

5. Instruction-Based Self-Testing of Processor Cores

   • Nektarios Kranitis
   • Antonis Paschalis
   • Yervant Zorian

   OriginalPaper Pages: 103 - 112

6. LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

   • Krishna Sekar
   • Sujit Dey

   OriginalPaper Pages: 113 - 123

7. Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

   • Erik H. Volkerink
   • Ajay Khoche
   • Klaus D. Hilliges

   OriginalPaper Pages: 125 - 135

8. Performance Comparison of VLV, ULV, and ECR Tests

   • Wanli Jiang
   • Eric Peterson

   OriginalPaper Pages: 137 - 147

9. A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

   • Vivekananda M. Vedula
   • Jacob A. Abraham
   • Raghuram Tupuri

   OriginalPaper Pages: 149 - 160

10. A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis

    • Shi-Yu Huang

    OriginalPaper Pages: 161 - 172

11. Statistical Tolerance Analysis for Assured Analog Test Coverage

    • Sule Ozev
    • Alex Orailoglu

    OriginalPaper Pages: 173 - 182

12. Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division

    • Takahiro J. Yamaguchi
    • Masahiro Ishida
    • Hirobumi Musha

    OriginalPaper Pages: 183 - 193

13. Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests

    • Said Hamdioui
    • Zaid Al-Ars
    • Mike Rodgers

    OriginalPaper Pages: 195 - 205

14. Testing and Diagnosis Methodologies for Embedded Content Addressable Memories

    • Jin-Fu Li
    • Ruey-Shing Tzeng
    • Cheng-Wen Wu

    OriginalPaper Pages: 207 - 215