Structural Fault Based Specification Reduction for Testing Analog Circuits Soon-Jyh ChangChung Len LeeJwu E. Chen OriginalPaper Pages: 571 - 581
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification Tom ChenAndre BaiC. Anderson OriginalPaper Pages: 583 - 594
Behavioral-Level DFT via Formal Operator Testability Measures Sandhya SeshadriMichael S. Hsiao OriginalPaper Pages: 595 - 611
Partial Scan Testing on the Register-Transfer Level Bruce S. GreeneSamiha Mourad OriginalPaper Pages: 613 - 626
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application Kuen-Jong LeeTsung-Chu Huang OriginalPaper Pages: 627 - 636
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM Chih-Wea WangChi-Feng WuHsiao-Ping Lin OriginalPaper Pages: 637 - 647