1. Editorial

   • Vishwani D. Agrawal

   Editorial Board Pages: 567 - 568

2. Test Technology Technical Council Newsletter

   Legacy Pages: 569 - 570

3. Structural Fault Based Specification Reduction for Testing Analog Circuits

   • Soon-Jyh Chang
   • Chung Len Lee
   • Jwu E. Chen

   OriginalPaper Pages: 571 - 581

4. Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification

   • Tom Chen
   • Andre Bai
   • C. Anderson

   OriginalPaper Pages: 583 - 594

5. Behavioral-Level DFT via Formal Operator Testability Measures

   • Sandhya Seshadri
   • Michael S. Hsiao

   OriginalPaper Pages: 595 - 611

6. Partial Scan Testing on the Register-Transfer Level

   • Bruce S. Greene
   • Samiha Mourad

   OriginalPaper Pages: 613 - 626

7. An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

   • Kuen-Jong Lee
   • Tsung-Chu Huang

   OriginalPaper Pages: 627 - 636

8. A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

   • Chih-Wea Wang
   • Chi-Feng Wu
   • Hsiao-Ping Lin

   OriginalPaper Pages: 637 - 647

9. 2002 Annual Index

   Authors Index Pages: 649 - 660