On IEEE P1500's Standard for Embedded Core Test Erik Jan MarinissenRohit KapurYervant Zorian OriginalPaper Pages: 365 - 383
An Integrated Framework for the Design and Optimization of SOC Test Solutions Erik LarssonZebo Peng OriginalPaper Pages: 385 - 400
On Concurrent Test of Core-Based SOC Design Yu HuangWu-Tung ChengSudhakar M. Reddy OriginalPaper Pages: 401 - 414
A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm Sandeep Koranne OriginalPaper Pages: 415 - 434
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs Erik Jan Marinissen OriginalPaper Pages: 435 - 454
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing Mounir BenabdenbiWalid MaroufiMeryem Marzouki OriginalPaper Pages: 455 - 473
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch Subhayu BasuIndranil SenguptaSudipta Bhawmik OriginalPaper Pages: 475 - 485
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores Tomokazu YonedaHideo Fujiwara OriginalPaper Pages: 487 - 501
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor Abhijit JasNur A. Touba OriginalPaper Pages: 503 - 514
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test Jin-Fu LiRuey-Shing TzengCheng-Wen Wu OriginalPaper Pages: 515 - 527
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores Li ChenXiaoliang BaiSujit Dey OriginalPaper Pages: 529 - 538
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs Mehrdad NouraniAmir Attarha OriginalPaper Pages: 539 - 554
