Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits Yukiya MiuraShuichi Seno OriginalPaper Pages: 109 - 120
Digital Window Comparator DfT Scheme for Mixed-Signal ICs Daniela De VenutoMichael J. OhletzBruno Riccò OriginalPaper Pages: 121 - 128
Enhanced Reduced Pin-Count Test for Full-Scan Design Harald VrankenTom WaayersDavid Lelouvier OriginalPaper Pages: 129 - 143
Hardware Generation of Random Single Input Change Test Sequences R. DavidP. GirardA. Virazel OriginalPaper Pages: 145 - 157
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST Hua-Guo LiangSybille HellebrandHans-Joachim Wunderlich OriginalPaper Pages: 159 - 170
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function Magnus EckersandFredrik FranzonKen Filliter OriginalPaper Pages: 171 - 177
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage M.B. SantosF.M. GonçalvesJ.P. Teixeira OriginalPaper Pages: 179 - 187
Synthesis of Scan Chains for Netlist Descriptions at RT-Level Yu HuangChien-Chung TsaiSudhakar M. Reddy OriginalPaper Pages: 189 - 201
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures V.A. ZivkovicR.J.W.T. TangelderH.G. Kerkhoff OriginalPaper Pages: 203 - 212
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip Vikram IyengarKrishnendu ChakrabartyErik Jan Marinissen OriginalPaper Pages: 213 - 230
Reusing Scan Chains for Test Pattern Decompression Rainer DorschHans-Joachim Wunderlich OriginalPaper Pages: 231 - 240
Diagnosis Strategies for Hardware or Software Systems Maisaa KhalilChantal RobachFranc Novak OriginalPaper Pages: 241 - 251
