1. Editorial

   • Vishwani D. Agrawal

   Editorial Board Pages: 203 - 203

2. Test Technology Technical Council Newsletter

   News Pages: 205 - 206

3. Guest Editorial

   • Paolo Prinetto
   • Joan Figueras

   Editorial Board Pages: 207 - 207

4. Test Challenges in Nanometer Technologies

   • Sandip Kundu
   • Sujit T. Zachariah
   • Rajesh Galivanche

   OriginalPaper Pages: 209 - 218

5. Current Testing Procedure for Deep Submicron Devices

   • Anton Chichkov
   • Dirk Merlier
   • Peter Cox

   OriginalPaper Pages: 219 - 224

6. Design for Delay Testability in High-Speed Digital ICs

   • H.G. Kerkhoff
   • H. Speek
   • M. Sachdev

   OriginalPaper Pages: 225 - 231

7. Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

   • A. Virazel
   • R. David
   • S. Pravossoudovitch

   OriginalPaper Pages: 233 - 241

8. On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages

   • Daniela De Venuto
   • Michael J. Ohletz

   OriginalPaper Pages: 243 - 253

9. Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST

   • F. Azaïs
   • S. Bernard
   • M. Renovell

   OriginalPaper Pages: 255 - 266

10. LEAP: An Accurate Defect-Free I_DDQ Estimator

    • Antoni Ferré
    • Joan Figueras

    OriginalPaper Pages: 267 - 274

11. Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ

    • Masaru Sanada

    OriginalPaper Pages: 275 - 281

12. A Discussion on Test Pattern Generation for FPGA—Implemented Circuits

    • M. Renovell
    • J.M. Portal
    • Y. Zorian

    OriginalPaper Pages: 283 - 290

13. Compressed Bit Fail Maps for Memory Fail Pattern Classification

    • Jőrg Vollrath
    • Ulf Lederer
    • Thomas Hladschik

    OriginalPaper Pages: 291 - 297

14. A System Level Boundary Scan Controller Board for VME Applications

    • Nuno Cardoso
    • Carlos Beltrán Almeida
    • José Carlos Da Silva

    OriginalPaper Pages: 299 - 310

15. RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

    • M.B. Santos
    • F.M. Gonçalves
    • J.P. Teixeira

    OriginalPaper Pages: 311 - 319

16. Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach

    • Franco Fummi
    • Marco Boschini
    • Elizabeth M. Rudnick

    OriginalPaper Pages: 321 - 330

17. A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

    • D. Berthelot
    • M.L. Flottes
    • B. Rouzeyre

    OriginalPaper Pages: 331 - 339

18. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

    • Sybille Hellebrand
    • Hua-Guo Liang
    • Hans-Joachim Wunderlich

    OriginalPaper Pages: 341 - 349

19. Application of Deterministic Logic BIST on Industrial Circuits

    • Gundolf Kiefer
    • Harald Vranken
    • Hans-Joachim Wunderlich

    OriginalPaper Pages: 351 - 362