Deterministic BIST with Partial Scan Gundolf KieferHans-Joachim Wunderlich OriginalPaper Pages: 169 - 177
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures Alfredo BensoSilvia CataldoYervant Zorian OriginalPaper Pages: 179 - 184
On Random Pattern Testability of Cryptographic VLSI Cores A. SchubertW. Anheier OriginalPaper Pages: 185 - 192
Low Power BIST by Filtering Non-Detecting Vectors S. ManichA. GabarróM. Santos OriginalPaper Pages: 193 - 202
Minimized Power Consumption for Scan-Based BIST Stefan GerstendörferHans-Joachim Wunderlich OriginalPaper Pages: 203 - 212
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations Jaan RaikRaimund Ubar OriginalPaper Pages: 213 - 226
Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology H. ManhaeveJ. VerfaillieJ.P. Cornil OriginalPaper Pages: 227 - 234
Experimental Results on BIC Sensors for Transient Current Testing R. PicosM. RocaE. García-Moreno OriginalPaper Pages: 235 - 241
Compaction of IDDQ Test Sequence Using Reassignment Method Toshiyuki MaedaKozo Kinoshita OriginalPaper Pages: 243 - 249
On Maximizing the Coverage of Catastrophic and Parametric Faults A.M. BrosaJ. Figueras OriginalPaper Pages: 251 - 258
Combining Functional and Structural Approaches for Switched-Current Circuit Testing M. RenovellF. AzaïsY. Bertrand OriginalPaper Pages: 259 - 267
Fault Simulation for Analog Circuits Under Parameter Variations Abdelhakim KhouasAnne Derieux OriginalPaper Pages: 269 - 278
Extending Fault-Based Testing to Microelectromechanical Systems S. MirB. CharlotB. Courtois OriginalPaper Pages: 279 - 288
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family M. RenovellJ.M. PortalY. Zorian OriginalPaper Pages: 289 - 299
