A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors Ta-Chung ChangVikram IyengarElizabeth M. Rudnick OriginalPaper Pages: 13 - 27
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology Pradip Bose OriginalPaper Pages: 29 - 48
A Buffer-Oriented Methodology for Microarchitecture Validation Noppanunt UtamaphethaiR.D. (Shawn) BlantonJohn Paul Shen OriginalPaper Pages: 49 - 65
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation Jian ShenJacob A. Abraham OriginalPaper Pages: 67 - 81
Verification Simulation Acceleration Using Code-Perturbation Byeong MinGwan Choi OriginalPaper Pages: 83 - 90
An Efficient Logic Equivalence Checker for Industrial Circuits Jaehong ParkCarl PixleyHyunwoo Cho OriginalPaper Pages: 91 - 106
Automatic Vector Generation Using Constraints and Biasing Jun YuanKurt ShultzAdnan Aziz OriginalPaper Pages: 107 - 120
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC™ Microprocessors Li-C. WangMagdy S. Abadir OriginalPaper Pages: 121 - 130
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability Sandhya SeshadriMichael S. Hsiao OriginalPaper Pages: 131 - 145
Oscillation Ring Delay Test for High Performance Microprocessors Wen Ching WuChung Len LeeMagdy S. Abadir OriginalPaper Pages: 147 - 155