1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 187 - 188

2. Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

   • Rajesh Ramadoss
   • Michael L. Bushnell

   OriginalPaper Pages: 189 - 205

3. A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification

   • M.A. El-Gamal
   • M.F. Abu El-Yazeed

   OriginalPaper Pages: 207 - 217

4. Testability of 2-Level AND/EXOR Circuits

   • Rolf Drechsler
   • Harry Hengster
   • Bernd Becker

   OriginalPaper Pages: 219 - 225

5. Built-in Self Test Based on Multiple On-Chip Signature Checking

   • Mohammed Fadle Abdulla
   • C.P. Ravikumar
   • Anshul Kumar

   OriginalPaper Pages: 227 - 244

6. A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata

   • María José López
   • Mar Martínez
   • Salvador Bracho

   OriginalPaper Pages: 245 - 258

7. Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

   • Huy Nguyen
   • Rabindra Roy
   • Abhijit Chatterjee

   OriginalPaper Pages: 259 - 272

8. Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs

   • Yuhai Ma
   • Wanchun Shi

   OriginalPaper Pages: 273 - 293

9. Experimental Results for Self-Dual Multi-Output Combinational Circuits

   • Vl. V. Saposhnikov
   • V. Moshanin
   • M. Goessel

   OriginalPaper Pages: 295 - 300

10. Testing of Oscillators

    • Andreas Rusznyak

    OriginalPaper Pages: 301 - 304

11. Erratum to An Algebra of Multiple Faults in RAMs

    • J.A. Brzozowski
    • H. Jürgensen

    OriginalPaper Pages: 305 - 306