1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 7 - 7

2. Guest Editorial

   • Christian Landrault

   OriginalPaper Pages: 11 - 11

3. Detection of Defects Using Fault Model Oriented Test Sequences

   • M. Renovell
   • F. Azaïs
   • Y. Bertrand

   OriginalPaper Pages: 13 - 22

4. Characterization of Floating Gate Defects in Analog Cells

   • Anna M. Brosa
   • Joan Figueras

   OriginalPaper Pages: 23 - 31

5. ICCQ: A Test Method for Analogue VLSI Using Local Current Sensors

   • Joop P.M. Van Lammeren

   OriginalPaper Pages: 33 - 38

6. A Low-Loss Built-In Current Sensor

   • Yukiya Miura
   • Hiroshi Yamazaki

   OriginalPaper Pages: 39 - 48

7. Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

   • Frank Pöhl
   • Walter Anheier

   OriginalPaper Pages: 49 - 55

8. Differential Thermal Testing: An Approach to its Feasibility

   • J. Altet
   • A. Rubio
   • H. Tamamoto

   OriginalPaper Pages: 57 - 66

9. Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters

   • Richard Rosing
   • Hans Kerkhoff
   • Manoj Sachdev

   OriginalPaper Pages: 67 - 74

10. Integrated Design and Test of Mixed-Signal Circuits

    • Nur Engin
    • Hans G. Kerkhoff
    • Han Speek

    OriginalPaper Pages: 75 - 83

11. Deterministic BIST with Multiple Scan Chains

    • Gundolf Kiefer
    • Hans-Joachim Wunderlich

    OriginalPaper Pages: 85 - 93

12. A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

    • P. Girard
    • C. Landrault
    • A. Virazel

    OriginalPaper Pages: 95 - 102

13. Incremental Testability Analysis for Partial Scan Selection and Design Transformations

    • Tianruo Yang
    • Zebo Peng

    OriginalPaper Pages: 103 - 113

14. BISTing Datapaths under Heterogeneous Test Schemes

    • D. Berthelot
    • M.L. Flottes
    • B. Rouzeyre

    OriginalPaper Pages: 115 - 123

15. Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach

    • Chris Feige
    • Jan Ten Pierick
    • Hans G. Kerkhoff

    OriginalPaper Pages: 125 - 131

16. From Design Validation to Hardware Testing: A Unified Approach

    • Ghassan Al-Hayek
    • Chantal Robach

    OriginalPaper Pages: 133 - 140

17. Exploiting Behavioral Information in Gate-Level ATPG

    • Silvia Chiusano
    • Fulvio Corno
    • Paolo Prinetto

    OriginalPaper Pages: 141 - 148

18. Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures

    • Octávio P. Dias
    • Isabel C. Teixeira
    • J. Paulo Teixeira

    OriginalPaper Pages: 149 - 158

19. SRAM-Based FPGAs: Testing the Embedded RAM Modules

    • M. Renovell
    • J.M. Portal
    • Y. Zorian

    OriginalPaper Pages: 159 - 167

20. Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach

    • Octavian-Dumitru Mocanu
    • Joan Oliver

    OriginalPaper Pages: 169 - 180