1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 219 - 219

2. Estimation of BIST Resources During High-Level Synthesis

   • Ishwar Parulkar
   • Sandeep K. Gupta
   • Melvin A. Breuer

   OriginalPaper Pages: 221 - 237

3. Testability Enhancement for Control-Flow Intensive Behaviors

   • Kelly A. Ockunzzi
   • Christos A. Papachristou

   OriginalPaper Pages: 239 - 257

4. Initialization of Sequential Circuits and its Application to ATPG

   • Jalal A. Wehbeh
   • Daniel G. Saab

   OriginalPaper Pages: 259 - 271

5. An IEEE 1149.1 Compliant Test Control Architecture

   • Debaditya Mukherjee
   • Melvin A. Breuer

   OriginalPaper Pages: 273 - 297

6. A Behavior Model for Next Generation Test Systems

   • Lee A. Shombert
   • John W. Sheppard

   OriginalPaper Pages: 299 - 314

7. Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

   • M. Psarakis
   • D. Gizopoulos
   • A. Paschalis

   OriginalPaper Pages: 315 - 319

8. A Method of Formal Verification of Cryptographic Circuits

   • Kanji Hirabayashi

   OriginalPaper Pages: 321 - 322