1. Editorial

   • Vishwani D. Agrawal

   Legacy Pages: 5 - 5

2. Guest Editorial

   • K.-T. Cheng
   • K.K. Saluja
   • H.-J. Wunderlich

   Legacy Pages: 7 - 8

3. Behavioral Testability Insertion for Datapath/Controller Circuits

   • Joan E. Carletta
   • Christos A. Papachristou

   OriginalPaper Pages: 9 - 28

4. Improving Testability of Non-Scan Designs during Behavioral Synthesis

   • M.L. Flottes
   • D. Hammad
   • B. Rouzeyre

   OriginalPaper Pages: 29 - 42

5. Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

   • Angela Krstić
   • Kwang-Ting Cheng

   OriginalPaper Pages: 43 - 54

6. Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

   • Marwan A. Gharaybeh
   • Michael L. Bushnell
   • Vishwani D. Agrawal

   OriginalPaper Pages: 55 - 67

7. BIST Pattern Generators Using Addition and Subtraction Operations

   • Albrecht P. Stroele

   OriginalPaper Pages: 69 - 80

8. Synthesis of Sequential Circuits by Redundancy Removal and Retiming

   • Hiroyuki Yotsuyanagi
   • Seiji Kajihara
   • Kozo Kinoshita

   OriginalPaper Pages: 81 - 92

9. Design for Testability Using State Distances

   • Frank F. Hsu
   • Janak H. Patel

   OriginalPaper Pages: 93 - 100