A Functional Decomposition Method for Redundancy Identification and Test Generation Michael L. BushnellJohn Giraldi OriginalPaper Pages: 175 - 195
Testing for Bounded Faults in RAMs R. DavidJ.A. BrzozowskiH. Jürgensen OriginalPaper Pages: 197 - 214
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations Debaleena DasMark Karpovsky OriginalPaper Pages: 215 - 229
Hierarchical Delay Test Generation C.P. RavikumarNitin AgrawalParul Agarwal OriginalPaper Pages: 231 - 244
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System Katsuyoshi MiuraKoji NakamaeHiromu Fujioka OriginalPaper Pages: 255 - 269
Symbolic Handling of Bridging Fault Effects Michele FavalliMarcello Dalpasso OriginalPaper Pages: 271 - 276
Workload Distribution in Fault Simulation Minesh B. AminBapiraju Vinnakota OriginalPaper Pages: 277 - 282