1. Editorial

   • Vishwani D. Agrawal

   Legacy Pages: 171 - 171

2. New Editorial Board Members

   Legacy Pages: 173 - 173

3. List of Reviewers

   Legacy Pages: 174 - 174

4. A Functional Decomposition Method for Redundancy Identification and Test Generation

   • Michael L. Bushnell
   • John Giraldi

   OriginalPaper Pages: 175 - 195

5. Testing for Bounded Faults in RAMs

   • R. David
   • J.A. Brzozowski
   • H. Jürgensen

   OriginalPaper Pages: 197 - 214

6. Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations

   • Debaleena Das
   • Mark Karpovsky

   OriginalPaper Pages: 215 - 229

7. Hierarchical Delay Test Generation

   • C.P. Ravikumar
   • Nitin Agrawal
   • Parul Agarwal

   OriginalPaper Pages: 231 - 244

8. Delay Test Generation: A Hardware Perspective

   • Jacob Savir

   OriginalPaper Pages: 245 - 254

9. Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System

   • Katsuyoshi Miura
   • Koji Nakamae
   • Hiromu Fujioka

   OriginalPaper Pages: 255 - 269

10. Symbolic Handling of Bridging Fault Effects

    • Michele Favalli
    • Marcello Dalpasso

    OriginalPaper Pages: 271 - 276

11. Workload Distribution in Fault Simulation

    • Minesh B. Amin
    • Bapiraju Vinnakota

    OriginalPaper Pages: 277 - 282

12. Module Level Weighted Random Patterns

    • Jacob Savir

    OriginalPaper Pages: 283 - 287