1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 101 - 101

2. A hierarchical test generation methodology for digital circuits

   • Debashis Bhattacharya
   • John P. Hayes

   OriginalPaper Pages: 103 - 123

3. Search strategy switching: A cost model and an analysis of backtracking

   • Hyoung B. Min
   • William A. Rogers

   OriginalPaper Pages: 125 - 137

4. Hierarchical multi-level fault simulation of large systems

   • Daniel G. Saab
   • Robert B. Mueller-Thuns
   • Jacob A. Abraham

   OriginalPaper Pages: 139 - 149

5. Detection of coupling faults in RAMs

   • J. A. Brzozowski
   • B. F. Cockburn

   OriginalPaper Pages: 151 - 162

6. An analytical approach to the partial scan problem

   • Arno Kunzmann
   • Hans-Joachim Wunderlich

   OriginalPaper Pages: 163 - 174

7. Multiple-output parity bit signature for exhaustive testing

   • Wen-Ben Jone
   • Sunil R. Das

   OriginalPaper Pages: 175 - 178