An optimal scheduling algorithm for testing interconnect using boundary scan Jung-Cheun LienMelvin A. Breuer OriginalPaper Pages: 117 - 130
Features of a Scan and Clock Resource chip for providing access to board-level test functions Bulent I. Dervisoglu OriginalPaper Pages: 107 - 115
Scan test architectures for digital board testers Matthew L. FichtenbaumGordon D. Robinson OriginalPaper Pages: 99 - 105
ATPG and diagnostics for boards implementing boundary scan Don SterbaAndy HallidayDon McClean OriginalPaper Pages: 89 - 98
Boundary scan test, test methodology, and fault modeling Frans De JongJosé S. MatosJosé M. Ferreira OriginalPaper Pages: 77 - 88
A language for describing boundary scan devices Kenneth P. ParkerStig Oresjo OriginalPaper Pages: 43 - 75
An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1 C. M. MaunderR. E. Tulloss OriginalPaper Pages: 27 - 42
IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status R. G. BennettsA. Osseyran OriginalPaper Pages: 11 - 25
A methodology for testability enhancement at layout level J. P. TeixeiraI. C. TeixeiraJ. Gonçalves OriginalPaper Pages: 287 - 299
A characterization of robust test-pairs for stuck-open faults Sreejit Chakravarty OriginalPaper Pages: 275 - 286
The probability of error detection in sequential circuits using random test vectors Asad A. IsmaeelMelvin A. Breuer OriginalPaper Pages: 245 - 256
Probabilistic fault grading based on activation checking and observability analysis Masahisa NakazawaSusumu NittaKanji Hirabayashi OriginalPaper Pages: 235 - 238
Probabilistic fault grading based on activation checking and observability analysis Masahisa NakazawaSusumu NittaKanji Hirabayashi OriginalPaper Pages: 235 - 238
Exact probabilistic testability measures for multi-output circuits P. CamuratiP. PrinettoM. Sonza Reorda OriginalPaper Pages: 229 - 234
Exact probabilistic testability measures for multi-output circuits P. CamuratiP. PrinettoM. Sonza Reorda OriginalPaper Pages: 229 - 234
Finite state machine synthesis with embedded test function Vishwani D. AgrawalKwang-Ting Cheng OriginalPaper Pages: 221 - 228
Finite state machine synthesis with embedded test function Vishwani D. AgrawalKwang-Ting Cheng OriginalPaper Pages: 221 - 228
Feedback-testing by using multiple input signature registers Martin Rudolph OriginalPaper Pages: 213 - 219
Feedback-testing by using multiple input signature registers Martin Rudolph OriginalPaper Pages: 213 - 219
Extended selection of switching target faults in CONT algorithm for test generation Yuzo TakamatsuKozo Kinoshita OriginalPaper Pages: 183 - 189
Extended selection of switching target faults in CONT algorithm for test generation Yuzo TakamatsuKozo Kinoshita OriginalPaper Pages: 183 - 189
Multiple-output parity bit signature for exhaustive testing Wen-Ben JoneSunil R. Das OriginalPaper Pages: 175 - 178
An analytical approach to the partial scan problem Arno KunzmannHans-Joachim Wunderlich OriginalPaper Pages: 163 - 174
Hierarchical multi-level fault simulation of large systems Daniel G. SaabRobert B. Mueller-ThunsJacob A. Abraham OriginalPaper Pages: 139 - 149
Search strategy switching: A cost model and an analysis of backtracking Hyoung B. MinWilliam A. Rogers OriginalPaper Pages: 125 - 137
A hierarchical test generation methodology for digital circuits Debashis BhattacharyaJohn P. Hayes OriginalPaper Pages: 103 - 123
Design considerations for Parallel pseudoRandom Pattern Generators Paul H. Bardell OriginalPaper Pages: 73 - 87
Optimizing error masking in BIST by output data modification Yervant ZorianVinod K. Agarwal OriginalPaper Pages: 59 - 71
Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection Y.-N. ShenF. Lombardi OriginalPaper Pages: 43 - 57
Fault-tolerance in balanced sorting networks Jianli SunJan GecseiEduard Cerny OriginalPaper Pages: 31 - 41
Redundancies and don't cares in sequential logic synthesis Srinivas DevadasHi-Keung Tony MaA. Richard Newton OriginalPaper Pages: 15 - 30
Differential fault simulation for sequential circuits Wu-Tung ChengMeng-Lin Yu OriginalPaper Pages: 7 - 13
