1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 03 December 2015 Pages: 421 - 422

2. Test Technology Newsletter

   News 06 November 2015 Pages: 423 - 424

   

3. 2014 JETTA-TTTC Best Paper Award

   Announcement 13 November 2015 Pages: 425 - 425

4. Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement

   • Tong-Yu Hsieh
   • Chih-Hao Wang
   • Tsung-Liang Chih

   OriginalPaper 13 November 2015 Pages: 427 - 441

   

5. Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range

   • Stéphane David-Grignot
   • Florence Azaïs
   • François Lefevre

   OriginalPaper 13 November 2015 Pages: 443 - 459

   

6. Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog Filters

   • Zewen Hu
   • Mingqing Xiao
   • Zhao Yang

   OriginalPaper 04 November 2015 Pages: 461 - 477

   

7. Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests

   • Suraj Sindia
   • Vishwani D. Agrawal

   OriginalPaper 07 November 2015 Pages: 479 - 489

   

8. Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points

   • Michał Tadeusiewicz
   • Andrzej Kuczyński
   • Stanisław Hałgas

   OriginalPaper Open access 28 November 2015 Pages: 491 - 502

   

9. A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

   • Nima Aghaee
   • Zebo Peng
   • Petru Eles

   OriginalPaper 16 November 2015 Pages: 503 - 523

   

10. Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection

    • Sezer Gören
    • Cemil Cem Gürsoy
    • Abdullah Yildiz

    OriginalPaper 31 October 2015 Pages: 525 - 536

    

11. Double Node Upsets Hardened Latch Circuits

    • Yuanqing Li
    • Haibin Wang
    • Jiangtao Xu

    OriginalPaper 17 November 2015 Pages: 537 - 548

    

12. Design and Implementation of an FPGA-Based Data/Timing Formatter

    • Yu-Yi Chen
    • Jiun-Lang Huang
    • Xuan-Lun Huang

    OriginalPaper 03 December 2015 Pages: 549 - 559

    

13. Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

    • Lixiang Li
    • Yuanqing Li
    • Li Chen

    OriginalPaper 14 November 2015 Pages: 561 - 568