Volume 28, Issue 1

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February 2012

Special Issue on Testing of Three-Dimensional Stacked Integrated Circuits

Issue Editors:

ERIK JAN MARINISSEN,
Yervant Zorian

15 articles in this issue

Editorial
Vishwani D. Agrawal
EditorialNotes 09 February 2012 Pages: 1 - 1
New Editors, 2012

Announcement 02 February 2012 Pages: 3 - 5
2011 JETTA Reviewers

Announcement 01 February 2012 Pages: 7 - 9
Test Technology Newsletter

News 02 February 2012 Pages: 11 - 12
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits
Erik Jan Marinissen
Yervant Zorian
EditorialNotes 04 February 2012 Pages: 13 - 14
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Mottaqiallah Taouil
Said Hamdioui
Erik Jan Marinissen
OriginalPaper Open access 08 December 2011 Pages: 15 - 25
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
Yi Lou
Zhuo Yan
Paul D. Franzon
OriginalPaper 03 November 2011 Pages: 27 - 38
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects
Sukeshwar Kannan
Bruce Kim
Byoungchul Ahn
OriginalPaper 03 November 2011 Pages: 39 - 51
Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits
Benjamin Backes
Colin McDonough
Robert E. Geer
OriginalPaper 09 September 2011 Pages: 53 - 62
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance
Valeriy Sukharev
Armen Kteyan
Rene Huebner
OriginalPaper 05 November 2011 Pages: 63 - 72
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Erik Jan Marinissen
Chun-Chuan Chi
Jouke Verbree
OriginalPaper Open access 13 December 2011 Pages: 73 - 92
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
Michael Buttrick
Sandip Kundu
OriginalPaper 03 November 2011 Pages: 93 - 101
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Brandon Noia
Krishnendu Chakrabarty
Erik Jan Marinissen
OriginalPaper 16 July 2011 Pages: 103 - 120
Scheduling Tests for 3D Stacked Chips under Power Constraints
Breeta SenGupta
Urban Ingelsson
Erik Larsson
OriginalPaper Open access 10 September 2011 Pages: 121 - 135
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Vladimir Pasca
Lorena Anghel
Mounir Benabdenbi
OriginalPaper 12 November 2011 Pages: 137 - 150

Volume 28, Issue 1

Editorial

New Editors, 2012

2011 JETTA Reviewers

Test Technology Newsletter

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits

Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs

Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Scheduling Tests for 3D Stacked Chips under Power Constraints

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems

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