1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 5 - 5

2. Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS

   • Nihal J. Godambe
   • C.-J. Richard Shi

   OriginalPaper Pages: 7 - 17

3. Layout Driven Selection and Chaining of Partial Scan Flip-Flops

   • Chau-Shen Chen
   • Tingting Hwang

   OriginalPaper Pages: 19 - 27

4. On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

   • Sebastian Fenn
   • Michael Gossel
   • David Taylor

   OriginalPaper Pages: 29 - 40

5. On-Chip Weighted Random Patterns

   • Jacob Savir

   OriginalPaper Pages: 41 - 50

6. IDDT Testing versus IDDQ Testing

   • Yinghua Min
   • Zhongcheng Li

   OriginalPaper Pages: 51 - 55

7. A Heuristic Measure to Maximize Detected Faults per Test

   • Kim T. Le
   • Kewal K. Saluja

   OriginalPaper Pages: 57 - 60

8. A Totally Self-Checking 1-out-of-3 Code Error Indicator

   • A. Paschalis
   • N. Gaitanis
   • P. Kostarakis

   OriginalPaper Pages: 61 - 66