A unified signal transition graph model for asynchronous control circuit synthesis Alexandre YakovlevLuciano LavagnoAlberto Sangiovanni-Vincentelli OriginalPaper Pages: 139 - 188
On the models for asynchronous circuit behaviour with OR causality Alexandre YakovlevMichael KishinevskyMarta Pietkiewicz-Koutny OriginalPaper Pages: 189 - 233
The incorporation of testing into formal verification: Direct, modular, and hierarchical correctness degrees Leo Marcus OriginalPaper Pages: 235 - 261