A formalization of a subset of VHDL in the Boyer-Moore logic David M. Russinoff OriginalPaper Pages: 7 - 25
A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL Peter T. BreuerLuis Sánchez FernándezCarlos Delgado Kloos OriginalPaper Pages: 27 - 51
Denotational semantics of a synchronous VHDL subset Dominique BorrioneAshraf Salem OriginalPaper Pages: 53 - 71
A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL Ralf ReetzThomas Kropf OriginalPaper Pages: 73 - 99
Translating VHDL into functional symbolic finite-state models Gert DöhmenRonald HerrmannHergen Pargmann OriginalPaper Pages: 125 - 148