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FPGA Implementations of SVM Classifiers: A Review

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Abstract

Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized for online classification in various real-time embedded applications. However, implementing SVM classification algorithm for an embedded system is challenging due to intensive and complicated computations required. Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010–2019. We performed a critical analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps. We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed, aiming to address such research gaps.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Auckland University of Technology, Auckland, 1010, New Zealand

    Shereen Afifi & Hamid GholamHosseini

  2. Department of IT and Software Engineering, Auckland University of Technology, Auckland, 1010, New Zealand

    Roopak Sinha

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  1. Shereen Afifi
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  2. Hamid GholamHosseini
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Afifi, S., GholamHosseini, H. & Sinha, R. FPGA Implementations of SVM Classifiers: A Review. SN COMPUT. SCI. 1, 133 (2020). https://doi.org/10.1007/s42979-020-00128-9

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