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Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

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Abstract

In this paper, a scalable throughput/area efficient hardware implementation of polynomial basis multiplication based on a digit-digit structure is presented. To compute multiplication operation, both input operands of the multiplier proceed in digit or word level. This property leads to reduce hardware consumption and critical path delay because the number of hardware resources and the critical path of the structure depends on digit size, which is lower than field size. Also, in the proposed digit-digit structure, based on the change of input digit size from low digit size to high digit size, the number of clock cycles and input words are different. Therefore, the multiplier can be flexible and scalable for different cryptographic considerations such as low-area and high-speed implementations. The proposed architecture is simple, low-area and also the product of area and delay in the structure is reduced and compared with existing works. So, the multiplier can be suitable for lightweight elliptic curve cryptosystems. The proposed digit-digit polynomial basis multiplier, for different digit sizes, has been successfully verified and implemented over binary finite fields \( {\mathbbm{F}}_{2^{163}} \) and \( {\mathbbm{F}}_{2^{233}} \) on Virtex-4 XC4VLX100 and Virtex-5 XC5VLX110 FPGAs. The comparison results with other previous structures of the polynomial basis multiplication verify that the proposed method has better improvement in terms of hardware consumption and execution time.

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  1. Department of Electrical Engineering, Ayatollah Boroujerdi University, Borujerd, 69199-69411, Iran

    Bahram Rashidi

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Rashidi, B. Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication. J Hardw Syst Secur 4, 120–135 (2020). https://doi.org/10.1007/s41635-019-00087-5

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