1 Introduction

With the extensive development of distributed generations like the wind power and photovoltaic power [1], as well as the ever increase of electric vehicles [2] and other DC loads, the DC system is drawing growing research interests due to advantages of low power loss, low investment, high reliability and so on [3, 4]. Supported by the evolution of the power-electronic technology [5], the flexible DC system is gaining popularity due to the advantages such as having an independent power control and being immune to commutation failure [6].

In engineering practice, the two-level voltage source converter (VSC) has been acknowledged as a viable device to integrate the distributed generations and DC loads. However, it has drawbacks such as high switching frequency, great switching power loss and poor power quality [7]. In this context, the idea of the MMC technique proposed in [8, 9] based on the modular design has a low switching frequency and better power quality [10].

Presently, several technical challenges to the development of DC system are confronting us, among which is the DC fault protection, including the fault detection and fault isolation.

The conventional converters, including the VSC and MMC, are not able to isolate the DC fault by themselves. Even the sub-modules in the converter are all blocked, the freewheeling diodes still act as an uncontrolled rectifier. Nowadays, there are typically three DC fault isolating methods.

1) The most ideal isolating method is interrupting the fault circuit by DC circuit breakers [11], which, however, are still not available for engineering application. Because there is no DC circuit breaker that could meet the requirements of interrupting capacity and action speed.

2) Due to the technical difficulty of the DC circuit breaker, an AC-circuit-breaker-based isolating method which could interrupt the DC fault circuit reliably was proposed in [12]. However, drawbacks of this method are obvious: slow response of the mechanical AC switch gear and large blackout area of the system.

3) Because of the reasons above, researchers are looking into the third method, i.e., eliminating the DC fault current by the converter. Reference [13] proposed a new MMC sub-module topology with DC fault current eliminating capability. After a DC fault happens, the fault current could be eliminated due to the reverse voltage from the capacitors in sub-modules. Reference [14] proposed the double-thyristor switch scheme which prevents the AC-side current contribution and allows the DC cable current freely decay to zero. However, the drawbacks like the thyristors withstanding high dv/dt in the normal operation should be taken into account. Reference [15] designed an isolating method which could reduce the level of dv/dt that thyristors have to withstand.

There has been a lot of work focusing on the fault isolation, however, the work on fault detection with identification capability is still rarely done. Therefore, it is necessary for us to make sense of DC fault transient characteristics. Reference [16] has done a detailed analysis for the DC faults in the two-level VSC based DC system. Because the topology of a MMC is different from the two-level VSC, it is important to investigate the transient characteristics of DC faults in a MMC-based DC system.

The works of this paper are as follows: Firstly, this paper analyzes the transient characteristics of a DC fault in the MMC-based DC system, which are different from the characteristics in a VSC-based one [16], providing the theoretical foundation for the design of the DC fault protection. Secondly, based on the fault characteristics, this paper discusses the technological difficulties of and requirements for the protection against DC faults in the DC system. In addition, the correctness of the theoretical analysis is verified by the simulation tests in MATLAB/Simulink.

2 Fault analysis for MMC-based DC system

Figure 1 shows a symmetrical bipolar DC system connected with the AC system by MMC. A MMC consists of three parallel-connected phase-units. One phase-unit comprises two arms, each with identical sub-modules (SMs) series-connected, as shown in Fig. 1. Owing to advantages like low switching losses, minor total harmonic distortion and modular design, etc, MMCs prove superior for constructing efficient DC distribution and transmission system.

Fig. 1
figure 1

Structure of MMC-based DC system

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Each SM is mainly comprised of two IGBTs (T1, T2), two freewheeling diodes (D1, D2), as well as a cell capacitor (C). Compared with the conventional two-level VSC, the only difference during the normal operation is the modulation strategy. MMC adopts the step pulse modulation which has advantages such as low switching losses and high waveform quality in contrast with the pulse-width modulating (PWM) that the two-level VSC adopts [9].

Fault current isolating technique and protection strategy are vital to the stability and reliability of the power grid. For this reason, it is essential to investigate DC fault transient characteristics and its influence on the DC-side system, AC-side system and converter. There are three kinds of DC faults, i.e., DC disconnection fault, DC pole-to-ground fault and DC pole-to-pole fault. Generally, the damage of a DC pole-to-pole fault is the severest [17]. So this paper analyzes the transient characteristics of a DC fault under the DC pole-to-pole fault condition.

In the field application, all the IGBTs would be soon turned off after a DC short-circuit fault. Fig. 2 illustrates the fault current path before and after turning off the IGBTs. Consequently, the DC fault transient process could be divided into three stages, namely ‘SMs normal operation stage’, ‘Initial stage after blocking SMs’ and ‘Uncontrolled rectifier stage’.

Fig. 2
figure 2

Equivalent circuit of DC pole-to-pole fault

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2.1 SMs normal operation stage

In this stage, the MMC is still working with the normal control strategy. The DC fault current is supplied by the AC-side source and cell capacitors in the on-state SMs. Therefore, the fault current flowing path could be illustrated as the red line in Fig. 2a, where we simply look into phase-A under a DC pole-to-pole fault condition, and the analysis can also be applied to phases B and C.

In Fig. 2a, u sa is the phase-A AC voltage; R s and L s are the equivalent impedance sum of the AC-side system and the transformer; R and L are the resistance and inductance of the arm reactors; R l and L l are the equivalent resistance and inductance of DC short-circuit cable. Generally, the DC system is earthed through large parallel resistors. Since the resistance of the fault circuit is very small, the parallel resistors can be ignored. Similarly, the distributed capacitor of the DC cable is also negligible compared with cell capacitors.

The short circuit can be simplified as the one in Fig. 3. It can be known that the numbers of on-state SMs in each arm are not equal when a DC fault happens, according to the normal operation control strategy. For the AC-side system, the DC fault should be considered as an unsymmetrical fault. And the solving of its transient process involves high order multidimensional differential equations, which makes it hard to obtain an analytic solution. So we opt for the numerical calculation method.

Fig. 3
figure 3

Equivalent fault circuit during SMs normal operation stage

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In Fig. 3, there are 16 energy storage components and 5 cut-sets only consisting of inductances, so we get 11 state variables. And we select 6 capacitor voltages (y 1~y 6) and 5 arm reactor currents (y 7~y 11) as the state variables. The forward directions of the state variables are also noted. Then the transient state can be expressed as

$$\left\{ \begin{array}{l} y_{1} - Ry_{7} - Ly_{7}^{\prime} - Ly_{8}^{\prime} - Ry_{8} + y_{2} \hfill \\ \quad= y_{3} - Ry_{9} - Ly_{9}^{\prime} - Ly_{10}^{\prime} + y_{4} \hfill \\ y_{1} - Ry_{7} - Ly_{7}^{\prime} - Ly_{8}^{\prime} - Ry_{8} + y_{2} = y_{5} - Ry_{11} \hfill \\ \quad- Ly_{11}^{\prime} - L\left( {y_{7}^{\prime} + y_{9}^{\prime} + y_{11}^{\prime} - y_{8}^{\prime} - y_{10}^{\prime}} \right) \hfill \\ - R\left( {y_{7} + y_{9} + y_{11} - y_{8} - y_{10} } \right) + y_{6} \hfill \\ y_{1} - Ry_{7} - Ly_{7}^{\prime} - Ly_{8}^{\prime} - Ry_{8} + y_{2} = \hfill \\\;R_{\text{l}} \left( {y_{7} + y_{9} + y_{11} } \right) + L_{\text{l}} \left( {y_{7}^{\prime} + y_{9}^{\prime} + y_{11}^{\prime}} \right) \hfill \\ u_{\text{sa}} - R_{\text{s}} \left( {y_{7} - y_{8} } \right) - L_{\text{s}} \left( {y_{7} - y_{8} } \right) - Ly_{7}^{\prime} - Ry_{7} + y_{1} \hfill \\\quad = u_{\text{sb}} - R_{\text{s}} \left( {y_{9} - y_{10} } \right) - L_{\text{s}} \left( {y_{9}^{\prime} - y_{10}^{\prime}} \right) - Ly_{9}^{\prime} - Ry_{9} + y_{3} \hfill \\ u_{\text{sa}} - R_{\text{s}} \left( {y_{7} - y_{8} } \right) - L_{\text{s}} \left( {y_{7} - y_{8} } \right) - Ly_{7}^{\prime} - Ry_{7} + y_{1} = u_{\text{sc}} \hfill \\\;\;\; - R_{\text{s}} \left( {y_{8} + y_{10} - y_{7} - y_{9} } \right) - L_{\text{s}} \left( {y_{8}^{\prime} + y_{10}^{\prime} - y_{7}^{\prime} - y_{9}^{\prime}} \right) \hfill \\\quad - Ly_{11}^{\prime} - Ry_{11} + y_{5} \hfill \\ C_{1} y_{1}^{\prime} = - y_{7} ,C_{2} y_{2}^{\prime} = - y_{8} ,C_{3} y_{3}^{\prime} = - y_{9} ,C_{4} y_{4}^{\prime} = - y_{10} \hfill \\ C_{5} y_{5}^{\prime} = - y_{11} ,C_{6} y_{6}^{\prime} = - \left( {y_{7} + y_{9} + y_{11} - y_{8} - y_{10} } \right) \hfill \\ \end{array} \right.$$
(1)

Equation (1) could be expressed by a matrix form showed as

$$\left[ \begin{array}{l} y_{1}^{\prime} \hfill \\ \vdots \hfill \\ y_{11}^{\prime} \hfill \\ \end{array} \right] = - A^{ - 1} B\left[ \begin{array}{l} y_{1} \hfill \\ \vdots \hfill \\ y_{11} \hfill \\ \end{array} \right] - A^{ - 1} C\left[ \begin{array}{l} u_{\text{sa}} \hfill \\ u_{\text{sb}} \hfill \\ u_{\text{sc}} \hfill \\ \end{array} \right]$$
(2)

where

$$A = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 & 0 & 0 & 0 & { - L} & { - L} & L & L & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & { - 2L} & L & { - L} & {2L} \\ 0 & 0 & 0 & 0 & 0 & 0 & { - \left( {L + L_{\text{l}} } \right)} & { - L} & {L_{\text{l}} } & 0 & { - L_{\text{l}} } \\ 0 & 0 & 0 & 0 & 0 & 0 & { - \left( {L_{\text{s}} + L} \right)} & {L_{\text{s}} } & {L_{\text{s}} + L} & { - L_{\text{s}} } & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & { - \left( {2L_{\text{s}} + L} \right)} & {2L_{\text{s}} } & { - L_{\text{s}} } & {L_{\text{s}} } & L \\ {C_{1} } & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & {C_{2} } & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & {C_{3} } & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & {C_{4} } & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & {C_{5} } & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & {C_{6} } & 0 & 0 & 0 & 0 & 0 \\ \end{array} } \right];$$
$$B = \left[ {\begin{array}{*{20}c} 1 & 1 & { - 1} & { - 1} & 0 & 0 & { - R} & { - R} & R & R & 0 \\ 1 & 1 & 0 & 0 & { - 1} & { - 1} & 0 & { - 2R} & R & { - R} & {2R} \\ 1 & 1 & 0 & 0 & 0 & 0 & { - \left( {R + R_{\text{l}} } \right)} & { - R} & { - R_{\text{l}} } & 0 & { - R_{\text{l}} } \\ 1 & 0 & { - 1} & 0 & 0 & 0 & { - \left( {R_{\text{s}} + R} \right)} & R & {R + R_{\text{s}} } & { - R_{\text{s}} } & 0 \\ 1 & 0 & 0 & 0 & { - 1} & 0 & { - \left( {2R_{\text{s}} + L} \right)} & {2R_{\text{s}} } & { - R_{\text{s}} } & {R_{\text{s}} } & R \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 & { - 1} & 1 & { - 1} & 1 \\ \end{array} } \right];$$
$$C = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & { - 1} & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & { - 1} & 0 & 0 & 0 & 0 & 0 & 0 \\ \end{array} } \right]^{\text{ T}} .$$

Then we can get the state equation format showed as

$$\left\{ \begin{aligned} y_{1}^{\prime} = f_{1} \left( {t,y_{1} ,y_{2} , \cdots ,\text{ }y_{11} } \right) \hfill \\ y_{2}^{\prime} = f_{2} \left( {t,y_{1} ,y_{2} , \cdots ,\text{ }y_{11} } \right) \hfill \\ \vdots \hfill \\ y_{11}^{\prime} = f_{11} \left( {t,y_{1} ,y_{2} , \cdots ,y_{11} } \right) \hfill \\ \end{aligned} \right.$$
(3)

The equations can be solved with the following Runge-Kutta formula

$$\left\{ \begin{array}{l} y_{i,n + 1} = y_{i,n} + \frac{h}{6}(k_{i1} + 2k_{i2} + 2k_{i3} + k_{i4} ) \hfill \\ k_{i1} = f_{i} (t_{n} ,y_{1n} ,y_{2n} , \cdots ,y_{11n} ) \hfill \\ k_{i2} = f_{i} (t_{n} + \frac{h}{2},y_{1n} + \frac{h}{2}k_{11} ,y_{2n} + \frac{h}{2}k_{21} , \cdots ,y_{11n} + \frac{h}{2}k_{m1} ) \hfill \\ k_{i3} = f_{i} (t_{n} + \frac{h}{2},y_{1n} + \frac{h}{2}k_{12} ,y_{2n} + \frac{h}{2}k_{22} , \cdots , y_{11n} + \frac{h}{2}k_{m2} ) \hfill \\ k_{i4} = f_{i} (t_{n} + h,y_{1n} + hk_{13} ,y_{2n} + hk_{23} , \cdots ,y_{11n} + hk_{m3} ) \hfill \\ i = 1,2, \cdots ,m \quad m = 11 \hfill \\ \end{array} \right.$$
(4)

where t n is the sampling sequence number; y i,n and y i,n+1 are the values of variable y i at the moments of t n and t n+1; h is the iterative calculation step.

By solving (3), we get the transient response of state variables. Figure 4 shows the simulation and calculation results, where i dc is the current flowing through the DC cable; i a_up is the upper arm current of phase A. (Here we set the fault happens at 10 km far from the exit of the MMC at t = 0 s, and the detailed parameters of the simulated system are shown as Appendix A.)

Fig. 4
figure 4

Fault current and di/dt of DC fault during SMs normal operation stage

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From Fig. 4, the theoretical analysis result of the fault current in this paper is very close to the simulation result. And the result also shows that not only the fault current goes up rapidly, but also the current variation rate di/dt keeps in a high level. As we know, the electric equipments may be unable to bear large short-circuit current, and a high di/dt would lead to the burning of IGBTs because of the local overheating. Therefore, in field application, if the fault detection is not fast enough to block the SMs, they would also be blocked at once the fault current or di/dt exceeds the threshold values of the self-protection for IGBTs. After that, the transient process would come into the next stage named as ‘Initial stage after blocking SMs blocked.

2.2 Initial stage after blocking SMs

In the circuit shown as Fig. 2b, freewheeling diodes D 2 will still bear a large fault current even if all IGBTs have been turned off. In this stage, the cell capacitors in the SMs are bypassed by the fault current, and thus would cease discharging. In other words, the cell capacitors discharge through and only in the first stage discussed in Section 2.1.

However, the reactors in the arms enable all freewheeling diodes marked as D2 to conduct continuously even after the capacitor discharge stops. Meanwhile, the AC-side source feeds the fault current through diodes and arm reactors. And the diodes enable the flow of the AC current all the time in spite of the unidirectional characteristic because of the freewheeling current from the reactors. In this case, the fault circuit is equivalent to that in Fig. 5.

Fig. 5
figure 5

Equivalent fault circuit during initial stage after blocking SMs

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According to the superposition theorem, the fault current is contributed by the current fed by the AC-side source and that provided by the arm reactor. Since the latter will keep all the diodes D2 working under this circumstance, the DC fault can be analyzed as a three-phase short circuit fault for the AC-side system, and the circuit is equivalent to that in Fig. 6a. Meanwhile, the discharge of the arm reactors is illustrated in Fig. 6b.

Fig. 6
figure 6

Fault current decomposition during initial stage after blocking SMs

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At the moment SMs are blocked, we assume the voltage and the current of phase A are u sa =U m sin(ωt+φ 0) and I sa0 respectively, and the current of the DC cable is I dc0. According to the solving method of the dynamic circuit, the phase-A current i sa and the DC cable current i dc are solved as

$$i_{\text{sa}} = I_{m} \sin \left( {\omega t + \varphi_{{_{0} }} - \varphi } \right) + \left[ {I_{\text{a0}} - I_{m} \sin \text{ }\left( {\varphi_{{_{0} }} - \varphi } \right)} \right]{\text{e}}^{{ - \text{ }\frac{t}{{\tau_{1} }}}}$$
(5)
$$i_{\text{dc}} = I_{{{\text{dc}}0}} {\text{e}}^{{ - \frac{t}{{\tau_{2} }}}}$$
(6)

where \(\text{I}_{m} = \frac{{U_{m} }}{{\sqrt {\left( {R_{\text{S}} + {R \mathord{\left/ {\vphantom {R 2}} \right. \kern-0pt} 2}} \right)^{2} + \left[ {\omega \left( {L_{\text{S}} + {L \mathord{\left/ {\vphantom {L 2}} \right. \kern-0pt} 2}} \right)} \right]^{2} } }}\); \(\varphi = { \arctan }\frac{{\omega \left( {L_{\text{S}} + \frac{L}{2}} \right)}}{{R_{\text{S}} + \frac{R}{2}}}\); \(\tau 1 = \frac{{L_{S} + \frac{L}{2}}}{{R_{S} + \frac{R}{2}}}\); \(\tau_{2} = \frac{{\frac{2L}{3} + L_{l} }}{{\frac{2R}{3} + R_{l} }}\).

The upper and lower arms of each phase in the MMC are strictly symmetrical, so the currents fed into the two arms by the ac-side source are equal in value. Likewise, i dc is evenly divided into the three phase-units. Therefore, the currents of the upper and lower arms of phase A (i a_up and i a_low) could be expressed as

$$\left\{ \begin{aligned} i_{{{\text{a{\_}up}}}} = \frac{{i_{\text{dc}} }}{3} + \frac{{i_{\text{sa}} }}{2} \hfill \\ i_{{{\text{a{\_}low}}}} = \frac{{i_{\text{dc}} }}{3} - \frac{{i_{\text{sa}} }}{2} \hfill \\ \end{aligned} \right.$$
(7)

Figure 7 shows the simulation and theoretical calculation results in this stage (t 1~t 2). And the former verifies the correctness of the theoretical analysis. It can also be seen that the current of DC cable decays gradually; the current at the AC side has a same waveform as a three-phase fault current; and the current of the arm in MMC is the superposition of the former two.

Fig. 7
figure 7

Results of initial stage after SMs being blocked

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Although all of SMs are blocked in this stage, instead of being reduced, the fault currents at the AC side and in the converter rise significantly, which would cause greater damage to the system, especially to the AC-side system and the diodes in the converter.

As shown in Fig. 7, the current of the upper arm of phase C arrives at zero at the time t 2, from when the diodes D2 in the corresponding arm begin to show the unidirectional characteristic. The three-phase fault state stops and the fault transient process would come into the next stage.

2.3 Uncontrolled rectifier stage

In this stage, the equivalent circuit is still shown as Fig. 5. However, with gradually decaying of the DC fault current i dc, there will be a time when each of the six arms has gone through a moment when its current reaches zero. And then we have to take consideration the unidirectional characteristic of the diodes D2 in all the six arms, which makes the MMC perform as an uncontrolled rectifier. So the last transient period can be considered as an uncontrolled rectifier stage approximatively.

Figure 8 shows the simulation results of the Stage 3. After one of the arm currents (i c_up in this case) arrives at zero, the remanent arms still have currents flowing through them, making the reactors in them keep on discharging and the freewheeling currents continue to decay. Gradually, the transient process gets into a stable state like an uncontrolled rectifier.

Fig. 8
figure 8

Whole process of DC pole-to-pole fault

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Due to the existence of the large reactor in each arm, there must be a commutation overlapping phenomenon in the MMC because of the freewheeling currents. Corresponding analysis method is similar to the way that we calculate the current in an uncontrolled rectifier which considers the effect of the inductance [18].

In summary, the fault currents at the DC side, ac side and in the converter would exist all the time. Because the equivalent impedance of the fault circuit is quite small, the currents would be considerably large.

3 Protection requirements for DC system

Figure 8 also shows the whole transient process of the DC pole-to-pole fault. According to the theoretical analysis and the simulation results, the transient process could be subdivided into three stages.

Stage 1: in this stage, SMs have not been blocked. The capacitors in the SMs and the ac-side sources feed the fault current synchronously. The arm current and the DC cable current rise rapidly. According to the transient characteristics of the DC fault, shortening this stage could reduce the overcurrent level significantly and do benefit to the recovery of the system.

Stage 2: in this stage, the reactors in the arms discharge continuously, and the AC-side sources feed three-phase fault current. For the whole DC system, especially the ac-side system and the devices in the MMC arms, the overcurrent in this stage is the most serious because of the three-phase fault current from the AC-side sources. So we must take measures to minimize the negative effects exerted on the system.

One method is to shorten the duration of this stage, which depends on the zero crossing time of the arm current: the earlier the arm current arrives at zero, the more quickly this stage will end. From (5)~(7), we can get the conclusion that the decay speed of the continuing current of the reactors have a bearing on the zero crossing time: the smaller the decay constants τ 1 and τ 2 are, then the earlier the arm current arrives at zero and the less time this stage lasts for. So we can shorten the duration of this stage by decreasing the value of τ 1 and τ 2 which could be realized by increasing the resistance in the fault circuit artificially.

Stage 3: in this stage, the operation state of the MMC is similar to that of an uncontrolled rectifier. Because the impedance of the DC short cable is minor, the fault current of the whole system is still comparatively large. However, the DC fault cannot be interrupted with high speed and security because there is no reliable commercial DC circuit breaker up to now.

As such, the protection strategy for the MMC based DC system must have following properties.

  1. 1)

    Observing the transient process of the DC fault, the overcurrent peak is dependent on the blocking moment of the IGBTs. In another word, if the fault detection is fast enough to provide a blocking signal for the SMs (before the IGBT self-protection), the overcurrent level of the system could be reduced significantly.

  2. 2)

    Even if all the IGBTs are turned off during a DC fault, the fault current exists all the time because the freewheeling diodes act as an uncontrolled rectifier. Therefore, under the circumstance that large capacity DC circuit breaker is still far away from the commercial application, the fast and efficient fault isolating method must be proposed, which is also based on the fast fault detection.

  3. 3)

    In a multi-terminal DC system, a similar transient process occurs at each converter station. Therefore, identifying the fault location using single-end information becomes a key technique.

4 Conclusions

This paper analyzes the transient characteristics of the DC fault. Theoretical analysis and simulation test show that the transient process can be divided into three stages. In Stage 1, the main damage is caused by the high di/dt level to the power-electronic devices and the overcurrent to the DC cable. In Stage 2 and 3, the severe overcurrent occurs at the AC side, DC side and in the converter itself. Consequently, it is essential to design an efficient DC protection strategy, especially the high speed fault detection, fast fault isolation and reliable fault identification.