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Modular Framework for Digital Twins: Development and Performance Analysis

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Abstract

The evolution of computing science and simulation tools led to the usage of virtualization in the industrial environment. Software models became relevant information providers for the evaluation of automation processes. Digital twins (DT) are an approach for intercommunicating physical and virtual systems. DTs are intended to improve the performance of real systems by using information generated on a virtual system (“twin”) that mirrors the behavior of physical parts. This work presents a distributed framework for DT implementation, which is composed of five integrated modules. The modules’ functions are process control , logical modeling, 3D visualization and data analysis. This paper presents the implementation and performance analysis of the DT framework. A discussion about its potentials and limitations is presented as well. The analysis focuses on timing and communication latency among the DT modules. A case study implementation, composed of the DTs of two manufacturing processes, is presented to validate the operation and to provide data for performance analysis of the DT framework.

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Notes

  1. “Legacy” or “dumb” devices are devices without the features of smart devices, such as networked operation, data processing capabilities and others.

  2. The only mandatory module is Process Control (OpenPLC).

  3. The custom application for 3D CAD animation.

  4. More details are provided in Sect. 5.1.2.

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Acknowledgements

The authors would like to thank the professor Fabrício Junqueira for the cooperation in the development of the animated 3D CAD model for the Sorting station.

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Correspondence to Rodrigo P. Rolle.

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This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001. Research also supported by grant 2018/19984-4, São Paulo Research Foundation (FAPESP)

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Rolle, R.P., Martucci, V.d.O. & Godoy, E.P. Modular Framework for Digital Twins: Development and Performance Analysis. J Control Autom Electr Syst 32, 1485–1497 (2021). https://doi.org/10.1007/s40313-021-00830-w

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  • DOI: https://doi.org/10.1007/s40313-021-00830-w

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