Abstract
Multiplier is a building block used in processor, embedded, Very Large-Scale Integration (VLSI) applications and integrated circuits. There are three main parameters of VLSI design lies in speed, area and power. Approximate computing is a developing one in digital design used to increase the performance. Many conventional methods are introduced for efficient approximate multiplier design. A new approximation multiplier design approach was presented with partial products of multiplier. A new approximate compressor was designed with higher power or speed for target precision. However, the designed approach failed to minimize the design complexity. In order to reduce power consumption and design complexity during the noise removal process, Genetic Fuzzy Optimized Approximate Multiplier based Non-Linear Anisotropic Diffusion Image Denoising (GFOAM-NLADID) Method is introduced. The key objective of the GFOAM-NLADID Method is to perform efficient approximate design using genetic fuzzy concepts for reducing the noise artifacts from input images. GFOAM-NLADID method used genetic fuzzy optimization algorithm to find optimal component (i.e., full adder type, compressor, and tree) for constructing the approximate multiplier design. The optimal component is selected after calculating the fuzzy fitness function. When the fitness function satisfies the fuzzy rule, the component is chosen for efficient design. When the criteria are not satisfied by the particular component, selection, crossover and mutation process is performed to choose the global optimal solution. By choosing the optimal component in GFOAM-NLADID Method, power consumption and design complexity level gets reduced. After designing the approximate multiplier, Non-Linear Anisotropic Diffusion Image Denoising process is carried out in GFOAM-NLADID Method to remove the noisy artifacts and to improve the image quality performance. This in turn helps to improve the peak signal-to-noise ratio performance by GFOAM-NLADID method. Experimental evaluation of GFOAM-NLADID Method is carried out with performance metrics such as power consumption, filtering time and peak signal-to-noise ratio compared to the state-of-the-art works.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Ahmadinejad M, Moaiyeri MH, Sabetzadeh F (2019) Energy and area efficient imprecise compressors for approximate multiplication at nanoscale. AEU Int J Electron Commun 110:1528–1559
Alouani I, Ahangari H, Ozturk O, Niar S (2018) A Novel heterogeneous approximate multiplier for low power and high performance. IEEE Embed Syst Lett 10(2):45–48
Ansari MS, Jiang H, Cockburn BF, Han J (2018) Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE J Emerg Select Topics Circuits Syst 8(3):404–416
Anusha G, Deepa P (2020) Design of approximate adders and multipliers for error tolerant image processing. Microprocess Microsyst Elsevier 72:1–7
Arulkarthick VJ, Rathinaswamy A (2020) Delay and area efficient approximate multiplier using reverse carry propagate full adder. Microprocess Microsyst Elsevier 74:1–17
Esposito D, Strollo AGM, Napoli E, Caro DD, Petra N (2018) Approximate multipliers based on new approximate compressors. IEEE Trans Circuits Syst I 65(12):4169–4182
Gillani GA, Hanif MA, Verstoep B, Gerez SH, Shafique M, Kokkeler ABJ (2019) MACISH: designing approximate MAC accelerators with internal-self-healing. IEEE Access 7:77142–77160
Ha M, Lee S (2018) Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embed Syst Lett 10(1):6–9
Hammad I, El-Sankary K (2018) Impact of approximate multipliers on VGG deep learning network. IEEE Access 6:60438–60444
Kumar S, Jha RK (2020) An FPGA-based design for a real-time image denoising using approximated fractional integrator. Multidimension Syst Signal Process 31:1317–1339
Leon V, Zervakis G, Soudris D, Pekmestzi K (2018). Approximate hybrid high radix encoding for energy-efficient inexact multipliers. IEEE Trans Very Large Scale Integr (VLSI) Syst, 26(3): 421-430
Lin L (2020) Low power consumption and reliability of wireless communication network in intelligent parking system. J Ambient Intell Human Comput. https://doi.org/10.1007/s12652-020-02183-9
Liu W, Xu J, Wang D, Wang C, Montuschi P, Lombardi F (2018) Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications. IEEE Trans Circuits Syst I Regul Pap 65(9):2856–2868
Liu W, Cao T, Yin P, Zhu Y, Wang C, Swartzlander EE (2019) Design and analysis of approximate redundant binary multipliers. IEEE Trans Comput 68(6):804–819
Loukrakpam M, Choudhury M (2019) Implementation of energy-efficient approximate multiplier with guaranteed worst case relative error. Microelectron J Elsevier 88:1–8
Mazahir S, Hasan O, Hafiz R, Shafique M (2017) Probabilistic error analysis of approximate recursive multipliers. IEEE Trans Comput 66(11):1982–1990
Osorio RR, Rodriguez G (2019) Truncated SIMD multiplier architecture for approximate computing in low-power programmable processors. IEEE Access 7:56353–56366
Prithivi Raj M, Kavithaa G (2020) Memristor based high speed and low power consumption memory design using deep search method. J Ambient Intell Human Comput. https://doi.org/10.1007/s12652-020-01817-2
Ranjbar F, Forghani Y, Bahrepour D (2018) High performance 8-bit approximate multiplier using novel 4:2 approximate compressors for fast image processing. Int J Integr Eng 10(1):114–133
Reddy KM, Vasantha MH, Kumar YBN, Dwivedi D (2019) Design and analysis of multiplier using approximate 4–2 compressor. AEU Int J Electron Commun Elsevier 107:89–97
Saadat H, Bokhari H, Parameswaran S (2018) Minimally biased multipliers for approximate integer and floating-point multiplication. IEEE Trans Comput Aided Des Integr Circuits Syst 37(11):2623–2635
Sabetzadeh F, Moaiyeri MH, Ahmadinejad M (2019) A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Trans Circuits Syst I Regul Pap 66(11):4200–4208
Strollo AGM, Napoli E, Caro DD, Petra N, Meo GD (2020). Comparison and extension of approximate 4–2 compressors for low-power approximate multipliers. IEEE Trans Circuits Syst–I Regular Pap, 67(9):3021–3029
Sunny A, Mathew BK, Dhanusha PB (2016) Area efficient high speed approximate multiplier with carry predictor. Procedia Technol Elsevier 24:1170–1177
Toan NV, Lee JG (2020) FPGA-based multi-level approximate multipliers for high-performance error-resilient applications. IEEE Access 8:25481–25497
Venkatachalam S, Ko SB (2017) Design of Power and Area Efficient Approximate Multipliers. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(5):1782–1786
Zendegani R, Kamal M, Bahadori M, Kusha AA, Pedram M (2017) RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(2), 393–401
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Chinnusamy, G.S., Shanmugasundaram, D. Genetic fuzzy optimized approximate multiplier design based non-linear anisotropic diffusion image denoising in VLSI. J Ambient Intell Human Comput (2021). https://doi.org/10.1007/s12652-021-03027-w
Received:
Accepted:
Published:
DOI: https://doi.org/10.1007/s12652-021-03027-w