Exploring novel characteristics of strain compensated SiGeC nanoscale MOSFET

Abstract

In the present work a precise but simple empirical model for single gate nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFET is proposed. The threshold voltage is calculated by solving the two-dimensional (2D) Poisson equation under befitting boundary conditions incorporating short-channel effects, the effect of strain, strained-silicon thin film thickness, and gate work function. The proposed empirical model provides results comparable with those obtained from 2D device simulation thereby establishing the extent of accuracy of our present model. The empirical model so developed correctly exhibits that the threshold voltage is reduced with the increase of strain in the silicon thin film. We have investigated, herewith our proposed model, the influences of various device parameters like: strain (with minute amount of carbon and significant amount of Ge), strained-silicon thin-film thickness and gate work function on the threshold voltage. The extent of equivalent Ge content enhances the performance of the proposed MOSFET in terms of better speed because of the carrier mobility enhancement due to addition of carbon atoms.