Abstract
The investigation of TFET for analog and RF application thus far is least focused. This paper presents an extensive investigation of TFET design space parameters on analog performance, and the study is more application perspective. The considered design space parameter is gate length. The impact of gate length on TFET performance is investigated using Technology Computer-Aided Design (TCAD) physical simulator. In this work, new observations have been made on cut-off frequency (fT) and gain-bandwidth product (fM). For lower gate length, transconductance is the predominant mechanism for the reduction of fT and fM. For higher gate length, gate-to-drain capacitance (Cgd) is the predominant mechanism for reducing fT and fM. Further, the lower gate length is not optimal for transconductance efficiency, while the higher gate length is not optimal for switching loss. The investigation in this paper shown that TFET with gate length of 10 nm to 20 nm has proved to be an optimal candidate for analog and RF application. It is the first time suggestion on the selection of TFET gate length for analog application.
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References
Zhijun Lyu , Hongliang Lv , Yuming Zhang , Yimen Zhang, Yi Zhu, Jiale Sun, Miao Li, and Bin Lu “A Novel High-Performance Planar InAs/GaSb Face-Tunneling FET With Implanted Drain for Leakage Current Reduction” IEEE Trans Electron Devices, Vol. 68, No. 3, 2021
Bennett RKA, Yoon Y (2021) IEEE Using “Anisotropic Insulators to Engineer the Electrostatics of Conventional and Tunnel Field-Effect Transistors”. IEEE Trans Electron Devices 68(2):February
Dwivedi P, Singh R, Sengar BS, Kumar A, Garg V (2021) A New Simulation Approach of Transient Response to Enhance the Selectivity and Sensitivity in Tunneling Field Effect Transistor-Based Biosensor. IEEE Sensors J 21(3)
Peng C, Yang Z, Lin Z, Wu X, Li X (2021) Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM. IEEE Trans Circ Syst—Ii: Express Briefs 68(1)
Duan X, Zhang J, Wang S, Li Y, Xu S, Hao Y (2018) A High-Performance Gate Engineered InGaN Dopingless Tunnel FET. IEEE Trans Electron Devices 65(3):1223
Xiaoling Duan , Jincheng Zhang, Shulong Wang, Yao Li, Shengrui Xu, and Yue Hao, Senior Member, IEEE “A High-Performance Gate Engineered InGaN Dopingless Tunnel FET” IEEE Trans Electron Devices, Vol. 65, No. 3, Pp.1223-1229 March 2018.
Amit Ranjan Trivedi, Sergio Carlo, and Saibal Mukhopadhyay “Exploring Tunnel-FET for Ultra Low Power Analog Applications: A Case Study on Operational Transconductance Amplifier”
Qing-Tai Zhao, Simon Richter, Christian Schulte-Braucks, Lars Knoll, Sebastian Blaeser, Gia Vinh Luong, Stefan Trellenkamp, Anna Schäfer, Andreas Tiedemann, Jean-Michel Hartmann, Konstantin Bourdelle, And Siegfried Mantl, “Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications,” Electron Device Soc Vol.3, No. 3, May 2015
B. Senale-Rodriguez and Y. Lu, “Perspectives of TFETs for low power analog ICs,” in Proc. Subthreshold Microelectron. Conf. (SubVT), Waltham, MA, USA, 2012, pp. 8–10.
P. G. Der Agopian et al., “Experimental comparison between trigate p-TFET and p-FinFET analog performance as a function of temperature,” IEEE Trans Electron Devices, vol. 60, no. 8, pp. 2493–2497, Aug. 2013.
Allen PE, Holberg DR (2002) CMOS Analog Circuit Design2nd edn. Oxford Univ. Press, New York
Mookerjea et al. 2009. Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications. In IEEE IEDM.
Hori, S., Maeda, T., Matsuno, N. and Hida, H. 2004. Lowpower widely tunable Gm-C filter with an adaptive DCblocking, triode-biased MOSFET transconductor. In IEEE JSSC
Wise, K. 2002. Wireless implantable Microsystems: coming breakthroughs in health care. In VLSI Symposium.
“A Low-Power Low Noise CMOS Amplifier for Neural Recording Applications”, In IEEE JSSC.
A. Mallik and A. Chattopadhyay, “Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications,” IEEE Trans Electron Devices, vol. 59, no. 4, pp. 888–894, Apr. 2012.
Verma N, Chandrakasan A (2007) An Ultra Low Energy 12-bit Rate-resolution Scalable SAR ADC for Wireless Sensor Nodes. In IEEE JSSC
Wan J, Le Royer C, Zaslavsky A, Crístoloveanu S (2010) Low-frequency noise behavior of tunneling field effect transistors. Appl Phys Lett
Kumar S, Goel E, Singh K, Singh B, Singh PK, Baral K, Jit S (2017) 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material DoubleGate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure. IEEE Trans on Electron Devices 64(3):960–968
C. Sheeja Herobin Rani & K. Bhoopathy Bagan & D. Nirmal & R. Solomon Roach, “Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness,” Silicon 10.1007/s12633-019-00328-w
Chen S, Liu H, Wang S, Li W, Wang X, Zhao L (2018) Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor. Nanoscale Res Lett 13(1):321
Chander S, Sinha SK, Kumar S, Singh PK, Baral K, Singh K, Jit S (2017) “Temperature analysis of Ge/Si heterojunction SOI-tunnel FET,” Elsevier. Superlattice Microst 110:162–170
Pindoo I (2021) Sanjeet Kumar Sinha, Sweta Chander Analog/RF Performance Analysis of Heterojunction Tunnel FET with Temperatute. Res Square. https://doi.org/10.21203/rs.3.rs-298331/v1
Anand S, Sarin R (2016) Analog and RF performance of doping-less tunnel FETs with Si0.55Ge0.45 source. J Comput Electron 15(3):850–856
Lakkas G (2016) MOSFET power losses and how they affect power-supply efficiency. Analog Appl J
Lee MJ, Choi WY (2011) Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid State Electron:110–114
Acknowledgements
The authors would like to thank Dr.P.Vimala, Associate Professor, Dayananda Sagar College of Engineering, Bangalore, India for providing the TCAD experimental facilities.
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Writing - literature search and analysis, original draft preparation: [J.E.Jeyanthi] [Dr.L.Arivazhagan], Idea of the article, Resources, Supervision: [T.S.Arun Samuel]
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Jeyanthi, J.E., Samuel, T.S.A. & Arivazhagan, L. Optimization of Design Space Parameters in Tunnel Fet for Analog/Mixed Signal Application. Silicon 14, 8233–8241 (2022). https://doi.org/10.1007/s12633-021-01591-6
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DOI: https://doi.org/10.1007/s12633-021-01591-6