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Investigation and Design of Stacked Oxide Polarity Gate JLTFET in the Presence of Interface Trap Charges for Analog/RF Applications

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Abstract

In this manuscript, the reliability of stacked oxide (SO) heterogeneous gate dielectric polarity gate junction less tunnel FET (PG JLTFET) has been investigated. The stacked oxide PG JLTFET (SO PG JLTFET) has been implemented using a high-k gate dielectric material (HfO2) layer that has been modeled on top of the silicon dioxide (SiO2) layer to improve the device performance. The stacked oxide based approach leads to decrement in leakage current at gate-channel interface and improves the channel interface maintenance quality of the device. The study has been conducted by analyzing the effect of both donor and acceptor interface charges (ITCs), present at the interface of silicon and oxide layer. Various DC and analog/RF performance parameters such as electric field, carrier concentration, device efficiency, cut off frequency (fT), input, output characteristics, higher order transconductance coefficients (gm2, gm3), transconductance frequency product (TFP) etc. have been analyzed. Besides, impact of ITCs on signal distortion and linearity for SO PG JLTFET using the parameters such as second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order input intercept point (IIP3), third order intermodulation distortion (IMD3) and 1-dB compression point have been studied in depth. The results obtained have also been compared with conventional polarity gate JLTFET (PG JLTFET). It has been observed, that the SO PG JLTFET is less sensitive to ITCs as compared to PG JLTFET.

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References

  1. Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, New York, NY, USA

    Book  Google Scholar 

  2. Kim S-H, Yokoyama M, Nakane R, Ichikawa O, Osada T, Hata M, Takenaka M, Takagi S (2014) High performance tri-gate extremely thin-body InAs-on-insulator MOSFETS with high short channel effect immunity and Vth tenability. IEEE Trans Electronic Devices 61(5):1354–1360

    Article  CAS  Google Scholar 

  3. Vishvakarma SK, Sharma D (2013) Precise analytical model for short channel quadruple gate-all-around MOSFET. IEEE Trans Nanotechnol 12(3):378–385

    Article  Google Scholar 

  4. Zhang Q, Seabaugh AC (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110

    Article  Google Scholar 

  5. Ionescu AM, Reil H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nature 479(7373):329–337

    Article  CAS  Google Scholar 

  6. Pal A, Dutta AK (2016) Analytical drain current modeling of double gate tunnel field- effect transistors. IEEE Trans Electron Devices 63(8):3213–3221

    Article  CAS  Google Scholar 

  7. Choi WY, Park B-G, Lee JD, Liu T-JK (2007) Tunneling field-effect transistor (TFETs) with subthreshold swing (SS) less than 60 mV/Dec. IEEE Electron Device Lett 28(8):743–745

    Article  CAS  Google Scholar 

  8. Zhang Q, Zhao W, Seabaugh A (2006) Low-sub threshold swing tunnel transistors. IEEE Trans Electron Device Lett 27(4):297–300

    Article  CAS  Google Scholar 

  9. Boucart K, Ionescu AM (2007) Double gate tunnel FET with high κκ gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  10. Sharma S, Kaur B (2020) Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction. IET Circuits, Devices & Systems 14(5):695–701

    Article  Google Scholar 

  11. Talukdar J, Rawat G, Choudhuri B, Singh K, Mummaneni K (2020 Oct) Device physics based analytical modeling for electrical characteristics of single gate extended source tunnel FET (SG-ESTFET). Superlattice Microst 13:106725

    Article  Google Scholar 

  12. Ahish S, Sharma D, Kumar YBN, Vasantha MH (2016) Performance enhancement of novel InAs/Si hetero double- gate tunnel FET using Gaussian doping. IEEE Trans Electron Devices 63(1):288–295

    Article  CAS  Google Scholar 

  13. Strangio S, Palestri P, Lanuzza M, Crupti F, Esseni D, Selmi L (2016) Assessment of InAs/AlGaSb tunnel FET virtual technology platform for low-power digital circuits. IEEE Trans Electron Devices 63(7):2749–2756

    Article  CAS  Google Scholar 

  14. Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE electron device letters 34(5):584–586

    Article  CAS  Google Scholar 

  15. Basak S, Asthana PK, Goswami Y, Ghosh B (2015) Leakage current reduction in junctionless tunnel FET using a lightly doped source. Applied Physics A 118(4):1527–1533

    Article  CAS  Google Scholar 

  16. Raad BR, Sharma D, Kondekar P, Nigam K, Yadav DS (2016) Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation. IEEE Transactions on Electron Devices 63(10):3950–3957

    Article  CAS  Google Scholar 

  17. Damrongplasit N, Shin C, Kim SH, Vega RA, Liu T-JK (2011) Study of random dopant fluctuation effects in germanium-source tunnel FETs. IEEE Trans Electron Devices 58(10):3541–3548

    Article  CAS  Google Scholar 

  18. Damrongplasit N, Kim SH, Liu T-JK (2013) Study of random dopant fluctuation induced variability in the raised- Ge-source TFET. IEEE Electron Device Lett. 34(2):184–186

    Article  CAS  Google Scholar 

  19. Chui GLCO (2013) Stochastic variability in silicon double gate lateral tunnel field-effect transistors. IEEE Trans Electron Devices 60(1):84–91

    Article  Google Scholar 

  20. Boucart, K., Ionescu, A.M., and Riess, W. (2010) A simulation-based study of sensitivity to parameter fluctuations of silicon tunnel FETs. Proceeding of European Solid State Device Research Conference 345-348

  21. Mayer, C.L.R.F. (2009) Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture 10th Int’l Conf. on Ultimate Integration of Silicon, Azchen, Germany 53-56

  22. Nigam K, Kondekar P, Sharma D, Raad BR (2016) A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism. Super Lattices and Microstructures 98:1–7

    Article  CAS  Google Scholar 

  23. Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Transactions on Electron Devices 58(3):677–683

    Article  CAS  Google Scholar 

  24. Wangkheirakpam VD, Bhowmick B, Pukhrambam PD (2020) Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises. Applied Physics A 126(10):1–10

    Article  Google Scholar 

  25. Gupta S, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Effect of Interface trap charges on performance variation of heterogeneous gate dielectric junction less-TFET. IEEE Transactions on Electron Devices 64(11):4731–4737

    Article  CAS  Google Scholar 

  26. Venkatesh P, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric. IEEE Trans Device Mater Reliab 17(1):245–252

    Article  CAS  Google Scholar 

  27. Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliab 16(2):227–234

    Article  CAS  Google Scholar 

  28. Sahu C, Singh J (2014) Charge-plasma based process variation immune junctionless transistor. IEEE Electron device letters 35(3):411–413

    Article  CAS  Google Scholar 

  29. ATLAS Device Simulation Software (2015) Silvaco Int.

  30. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8):743–745

    Article  CAS  Google Scholar 

  31. Esseni D, Guglielmini M, Kapidani B, Rollo T, Alioto M (2014) Tunnel FETs for ultralow voltage digital VLSI circuits: part I—device–circuit interaction and evaluation at device level. IEEE Trans. Very Large Scale Integr. (VLSI) Syst 22(12):2488–2498

    Article  Google Scholar 

  32. Kondekar PN, Nigam K, Pandey S, Sharma D (2016) Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications. IEEE Transactions on Electron Devices 64(2):412–418

    Article  Google Scholar 

  33. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) Nanotube tunneling FET with a core source for ultrasteep subthreshold swing: a simulation study. IEEE Trans Electron Devices 66(10):4425–4432

    Article  CAS  Google Scholar 

  34. Joshi T, Singh Y, Singh B (2020) Extended-source double-gate tunnel FET with improved DC and analog/RF performance. IEEE Transactions on Electron Devices 67(4):1873–1879

  35. Kato K, Jo KW, Matsui H, Tabata H, Mori T, Morita Y, Takagi S (2020) P-channel TFET operation of bilayer structures with type-II heterotunneling junction of oxide-and group-IV semiconductors. IEEE Transactions on Electron Devices 67(4):1880–1886

    Article  CAS  Google Scholar 

  36. Kato K, Matsui H, Tabata H, Mori T, Morita Y, Matsukawa T, Takagi S (2020) Improvement in electrical characteristics of ZnSnO/Si bilayer TFET by W/Al2O3 gate stack. IEEE Journal of the Electron Devices Society 8:341–345

    Article  CAS  Google Scholar 

  37. Zhang A, Mei J, Zhang L, He H, He J, Chan M (2012) Numerical study on dual material gate nanowire tunnel field-effect transistor. IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC) 1–5

  38. Cheng W, Liang R, Xu G, Yu G, Zhang S, Yin H, Xu J (2020) Fabrication and characterization of a novel Si line tunneling TFET with high drive current. IEEE Journal of the Electron Devices Society 8:336–340

  39. Yang Y, Tong X, Yang LT, Guo PF, Fan L, Yeo YC (2010) Tunneling field effect transistor: capacitance components and modeling. IEEE Electron Device Lett. 31(7):752–754

    Article  CAS  Google Scholar 

  40. Chaujar R, Kaur R, Saxena M, Gupta M, Gupta RS (2008) Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design. Superlattice Microst 44(2):143–152

    Article  CAS  Google Scholar 

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Acknowledgements

The authors would like to thank the JIIT authority for providing continuous support related to research work.

Availability of Data and Material (Data Transparency)

All the data taken from another resource has been given the corresponding reference. The data, for which reference is not provided, is the original data.

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The code has been implemented on 2-D silvaco ATLAS device simulator.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, 201304, India

    Kaushal Nigam, Sajai Vir Singh & Priyanka Kwatra

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  1. Kaushal Nigam
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  2. Sajai Vir Singh
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  3. Priyanka Kwatra
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Kaushal Nigam, Sajai Vir Singh and Priyanka Kwatra in this work contributed equally to the design and implementation of the research, to the analysis of the results and to the writing of the manuscript.

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Correspondence to Priyanka Kwatra.

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Kaushal Nigam, Sajai Vir Singh and Priyanka Kwatra state that there are no conflicts of interest. This article does not contain any studies with human or animal subjects.

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Nigam, K., Singh, S.V. & Kwatra, P. Investigation and Design of Stacked Oxide Polarity Gate JLTFET in the Presence of Interface Trap Charges for Analog/RF Applications. Silicon 14, 3963–3980 (2022). https://doi.org/10.1007/s12633-021-01162-9

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