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A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices

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Abstract

Through the age of nanoelectronics, device dimensions are curbed, and the size of transistors is rapidly reduced. Scaling down transistors results in high-speed switching, higher density, reduced power consumption, lower transistor costs. Some of the critical issues facing scaling down transistor sizes such as punch-through effect, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage roll-off, leakage current effects various proposed structure. The evolution of the semiconductor industry from the appropriate methods CMOS into a proposed structure called TFET. The TFET is a suitable method as a critical part of the power usage in circuit boards that achieves its target to meet reverse sub-threshold slope (SS) below the temperature limit (60 mV/dec in room temperature) with often a lower drive current implicitly than a MOSFET. In this study, an effort has been made to bring the roadmap of various TFET structures like Single gated TFET, Double gated TFET, Tri gated TFET, and, finally, Heterojunction TFET.

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Contributions

Writing - literature search and analysis, original draft preparation: [J.E.Jeyanthi] [A.Sharon Geege], Idea of the article, Resources, Supervision: [T.S.Arun Samuel], Checked the comparison results and validation: [P.Vimala].

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  1. Department of ECE, National Engineering College, Kovilpatti, India

    J. E. Jeyanthi, T. S. Arun Samuel & A. Sharon Geege

  2. Department of ECE, Dayananda Sagar College of Engineering, Bangalore, India

    P. Vimala

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  1. J. E. Jeyanthi
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  3. A. Sharon Geege
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Jeyanthi, J.E., Samuel, T.S.A., Geege, A.S. et al. A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices. Silicon 14, 3185–3197 (2022). https://doi.org/10.1007/s12633-021-01148-7

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