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Linearity Parameters Evaluation due to Lateral Straggle in Ge-Source DMDG-TFET

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Abstract

TFET is very favourable device than MOSFET in terms of low power design and applications. The accurate fabrication of device results in satisfactory electrical characteristics. The diffusion of source/drain regions through the ion implantation technique, extent to the channel section, which eventually changes the behaviour of device. In this letter, the linearity behaviour of Ge-source dual material double gate (DMDG) TFET is highlighted for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The linearity parameters such as higher order harmonics (gm2 and gm3), voltage intercept point (VIP2 and VIP3), input intercept power (IIP3), intermodulation distortion (IMD3), and 1-dB compression point are studied in Ge-source DMDG-TFET taking σ as parameter.

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Funding

The authors acknowledge the funding by Science & Engineering Research Board, Govt. of India (Sanction Reference. No. SRG/2019/000628).

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  1. Electronics and Communication Engineering Department, Malaviya National Institute of Technology Jaipur, Jaipur, Rajasthan, 302017, India

    Rajesh Saha

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  1. Rajesh Saha
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All the works in this paper have done by Rajesh Saha.

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Correspondence to Rajesh Saha.

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Saha, R. Linearity Parameters Evaluation due to Lateral Straggle in Ge-Source DMDG-TFET. Silicon 14, 567–571 (2022). https://doi.org/10.1007/s12633-020-00859-7

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